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authorAndreas Hansson <andreas.hansson@arm.com>2012-02-24 11:42:00 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2012-02-24 11:42:00 -0500
commit9f07d2ce7ecf435b9a1946f15fb3491bb4636637 (patch)
tree33f66ff6c258214a6b266b3cc582a52774935ae2 /src/arch
parentef4af8cec8b1826abff5b92b9fec32f7c2818372 (diff)
downloadgem5-9f07d2ce7ecf435b9a1946f15fb3491bb4636637.tar.xz
CPU: Round-two unifying instr/data CPU ports across models
This patch continues the unification of how the different CPU models create and share their instruction and data ports. Most importantly, it forces every CPU to have an instruction and a data port, and gives these ports explicit getters in the BaseCPU (getDataPort and getInstPort). The patch helps in simplifying the code, make assumptions more explicit, andfurther ease future patches related to the CPU ports. The biggest changes are in the in-order model (that was not modified in the previous unification patch), which now moves the ports from the CacheUnit to the CPU. It also distinguishes the instruction fetch and load-store unit from the rest of the resources, and avoids the use of indices and casting in favour of keeping track of these two units explicitly (since they are always there anyways). The atomic, timing and O3 model simply return references to their already existing ports.
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