scons: Fix up numerous warnings about name shadowing

This patch address the most important name shadowing warnings (as
produced when using gcc/clang with -Wshadow). There are many
locations where constructor parameters and function parameters shadow
local variables, but these are left unchanged.

4 files changed, 3 insertions, 14 deletions

diff --git a/src/arch/alpha/interrupts.hh b/src/arch/alpha/interrupts.hh
index ce3108d79..5749a1f0d 100644
--- a/src/arch/alpha/interrupts.hh
+++ b/src/arch/alpha/interrupts.hh
@@ -158,11 +158,10 @@ class Interrupts : public SimObject
             }
         }
 
-        uint64_t interrupts = intstatus;
-        if (interrupts) {
+        if (intstatus) {
             for (uint64_t i = INTLEVEL_EXTERNAL_MIN;
                  i < INTLEVEL_EXTERNAL_MAX; i++) {
-                if (interrupts & (ULL(1) << i)) {
+                if (intstatus & (ULL(1) << i)) {
                     // See table 4-19 of 21164 hardware reference
                     ipl = i;
                     summary |= (ULL(1) << i);
diff --git a/src/arch/alpha/stacktrace.cc b/src/arch/alpha/stacktrace.cc
index 7c23489a3..8c0e85af4 100644
--- a/src/arch/alpha/stacktrace.cc
+++ b/src/arch/alpha/stacktrace.cc
@@ -197,7 +197,7 @@ StackTrace::trace(ThreadContext *_tc, bool is_call)
             return;
         }
 
-        bool kernel = sys->kernelStart <= pc && pc <= sys->kernelEnd;
+        kernel = sys->kernelStart <= pc && pc <= sys->kernelEnd;
         if (!kernel)
             return;
 
diff --git a/src/arch/arm/insts/vfp.cc b/src/arch/arm/insts/vfp.cc
index 6e15282f8..015247d68 100644
--- a/src/arch/arm/insts/vfp.cc
+++ b/src/arch/arm/insts/vfp.cc
@@ -995,7 +995,6 @@ FpOp::binaryOp(FPSCR &fpscr, fpType op1, fpType op2,
 
     // Get NAN behavior right. This varies between x86 and ARM.
     if (std::isnan(dest)) {
-        const bool single = (sizeof(fpType) == sizeof(float));
         const uint64_t qnan =
             single ? 0x7fc00000 : ULL(0x7ff8000000000000);
         const bool nan1 = std::isnan(op1);
@@ -1066,7 +1065,6 @@ FpOp::unaryOp(FPSCR &fpscr, fpType op1, fpType (*func)(fpType),
 
     // Get NAN behavior right. This varies between x86 and ARM.
     if (std::isnan(dest)) {
-        const bool single = (sizeof(fpType) == sizeof(float));
         const uint64_t qnan =
             single ? 0x7fc00000 : ULL(0x7ff8000000000000);
         const bool nan = std::isnan(op1);
diff --git a/src/arch/arm/isa/formats/fp.isa b/src/arch/arm/isa/formats/fp.isa
index 0cb27d7f1..6d779e541 100644
--- a/src/arch/arm/isa/formats/fp.isa
+++ b/src/arch/arm/isa/formats/fp.isa
@@ -1570,13 +1570,6 @@ let {{
                 }
               case 0x6:
                 if (b == 0xc) {
-                    const IntRegIndex vd =
-                        (IntRegIndex)(2 * (bits(machInst, 15, 12) |
-                                           (bits(machInst, 22) << 4)));
-                    const IntRegIndex vm =
-                        (IntRegIndex)(2 * (bits(machInst, 3, 0) |
-                                           (bits(machInst, 5) << 4)));
-                    unsigned size = bits(machInst, 19, 18);
                     return decodeNeonSTwoShiftUSReg<NVshll>(
                             size, machInst, vd, vm, 8 << size);
                 } else {
@@ -1866,7 +1859,6 @@ let {{
           case 0x3:
             const bool up = (bits(machInst, 23) == 1);
             const uint32_t imm = bits(machInst, 7, 0) << 2;
-            RegIndex vd;
             if (single) {
                 vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
                                           (bits(machInst, 22)));