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author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:05 -0500 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:05 -0500 |
commit | c981a4de2b317a3e5dd6813e809973c7d6734f41 (patch) | |
tree | 3f0b326d5957478f429980e8ffd8a002076b4037 /src/arch | |
parent | 57443a2144c6f446c7b7a3de7389ae794d591330 (diff) | |
download | gem5-c981a4de2b317a3e5dd6813e809973c7d6734f41.tar.xz |
ARM: Add base classes suitable for the REV* instructions.
Diffstat (limited to 'src/arch')
-rw-r--r-- | src/arch/arm/insts/misc.cc | 11 | ||||
-rw-r--r-- | src/arch/arm/insts/misc.hh | 14 | ||||
-rw-r--r-- | src/arch/arm/isa/templates/misc.isa | 21 |
3 files changed, 46 insertions, 0 deletions
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc index 588586e00..3547c6712 100644 --- a/src/arch/arm/insts/misc.cc +++ b/src/arch/arm/insts/misc.cc @@ -142,3 +142,14 @@ MsrRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const printReg(ss, op1); return ss.str(); } + +std::string +RevOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +{ + std::stringstream ss; + printMnemonic(ss); + printReg(ss, dest); + ss << ", "; + printReg(ss, op1); + return ss.str(); +} diff --git a/src/arch/arm/insts/misc.hh b/src/arch/arm/insts/misc.hh index 105a90c37..ae8d20e79 100644 --- a/src/arch/arm/insts/misc.hh +++ b/src/arch/arm/insts/misc.hh @@ -94,4 +94,18 @@ class MsrRegOp : public MsrBase std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; +class RevOp : public PredOp +{ + protected: + IntRegIndex dest; + IntRegIndex op1; + + RevOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, + IntRegIndex _dest, IntRegIndex _op1) : + PredOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1) + {} + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; +}; + #endif diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa index a19228b3b..566d0a8dd 100644 --- a/src/arch/arm/isa/templates/misc.isa +++ b/src/arch/arm/isa/templates/misc.isa @@ -98,3 +98,24 @@ def template MsrImmConstructor {{ %(constructor)s; } }}; + +def template RevOpDeclare {{ +class %(class_name)s : public %(base_class)s +{ + protected: + public: + // Constructor + %(class_name)s(ExtMachInst machInst, + IntRegIndex _dest, IntRegIndex _op1); + %(BasicExecDeclare)s +}; +}}; + +def template RevOpConstructor {{ + inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + IntRegIndex _dest, IntRegIndex _op1) + : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1) + { + %(constructor)s; + } +}}; |