diff options
author | Gabe Black <gblack@eecs.umich.edu> | 2013-01-04 19:00:45 -0600 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2013-01-04 19:00:45 -0600 |
commit | e17c375ddd32fbbef55a96c446a4b98b20df2ad5 (patch) | |
tree | 42e917087dc0887f0aed3d74bad6196f27ab0d0c /src/arch | |
parent | d1965af22045d2a62b1cd1bc473b836413d79b46 (diff) | |
download | gem5-e17c375ddd32fbbef55a96c446a4b98b20df2ad5.tar.xz |
Decoder: Remove the thread context get/set from the decoder.
This interface is no longer used, and getting rid of it simplifies the
decoders and code that sets up the decoders. The thread context had been used
to read architectural state which was used to contextualize the instruction
memory as it came in. That was changed so that the state is now sent to the
decoders to keep locally if/when it changes. That's significantly more
efficient.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Diffstat (limited to 'src/arch')
-rw-r--r-- | src/arch/alpha/decoder.hh | 18 | ||||
-rw-r--r-- | src/arch/arm/decoder.cc | 1 | ||||
-rw-r--r-- | src/arch/arm/decoder.hh | 17 | ||||
-rw-r--r-- | src/arch/arm/isa.cc | 2 | ||||
-rw-r--r-- | src/arch/mips/decoder.hh | 16 | ||||
-rw-r--r-- | src/arch/power/decoder.hh | 18 | ||||
-rw-r--r-- | src/arch/sparc/decoder.hh | 18 | ||||
-rw-r--r-- | src/arch/sparc/isa.cc | 3 | ||||
-rw-r--r-- | src/arch/x86/decoder.cc | 1 | ||||
-rw-r--r-- | src/arch/x86/decoder.hh | 16 |
10 files changed, 9 insertions, 101 deletions
diff --git a/src/arch/alpha/decoder.hh b/src/arch/alpha/decoder.hh index ef2f5856c..45e737e52 100644 --- a/src/arch/alpha/decoder.hh +++ b/src/arch/alpha/decoder.hh @@ -36,36 +36,20 @@ #include "cpu/static_inst.hh" #include "sim/full_system.hh" -class ThreadContext; - namespace AlphaISA { class Decoder { protected: - ThreadContext *tc; - // The extended machine instruction being generated ExtMachInst ext_inst; bool instDone; public: - Decoder(ThreadContext * _tc) : tc(_tc), instDone(false) + Decoder() : instDone(false) {} - ThreadContext * - getTC() - { - return tc; - } - - void - setTC(ThreadContext * _tc) - { - tc = _tc; - } - void process() { } diff --git a/src/arch/arm/decoder.cc b/src/arch/arm/decoder.cc index b5a73d68b..e957ce0e7 100644 --- a/src/arch/arm/decoder.cc +++ b/src/arch/arm/decoder.cc @@ -32,7 +32,6 @@ #include "arch/arm/isa_traits.hh" #include "arch/arm/utility.hh" #include "base/trace.hh" -#include "cpu/thread_context.hh" #include "debug/Decoder.hh" namespace ArmISA diff --git a/src/arch/arm/decoder.hh b/src/arch/arm/decoder.hh index 9099e3e2e..83a16da4c 100644 --- a/src/arch/arm/decoder.hh +++ b/src/arch/arm/decoder.hh @@ -39,15 +39,12 @@ #include "base/types.hh" #include "cpu/static_inst.hh" -class ThreadContext; - namespace ArmISA { class Decoder { protected: - ThreadContext * tc; //The extended machine instruction being generated ExtMachInst emi; MachInst data; @@ -72,23 +69,11 @@ class Decoder foundIt = false; } - Decoder(ThreadContext * _tc) : tc(_tc), data(0), - fpscrLen(0), fpscrStride(0) + Decoder() : data(0), fpscrLen(0), fpscrStride(0) { reset(); } - ThreadContext * getTC() - { - return tc; - } - - void - setTC(ThreadContext * _tc) - { - tc = _tc; - } - void process(); //Use this to give data to the decoder. This should be used diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 0df50a85e..ee2799147 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -381,7 +381,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) fpscrMask.n = ones; newVal = (newVal & (uint32_t)fpscrMask) | (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); - tc->getDecodePtr()->setContext(newVal); + tc->getDecoderPtr()->setContext(newVal); } break; case MISCREG_CPSR_Q: diff --git a/src/arch/mips/decoder.hh b/src/arch/mips/decoder.hh index 4857eb353..080614dee 100644 --- a/src/arch/mips/decoder.hh +++ b/src/arch/mips/decoder.hh @@ -37,34 +37,20 @@ #include "base/types.hh" #include "cpu/static_inst.hh" -class ThreadContext; - namespace MipsISA { class Decoder { protected: - ThreadContext * tc; //The extended machine instruction being generated ExtMachInst emi; bool instDone; public: - Decoder(ThreadContext * _tc) : tc(_tc), instDone(false) + Decoder() : instDone(false) {} - ThreadContext *getTC() - { - return tc; - } - - void - setTC(ThreadContext *_tc) - { - tc = _tc; - } - void process() { diff --git a/src/arch/power/decoder.hh b/src/arch/power/decoder.hh index 60fc8ca75..830636aed 100644 --- a/src/arch/power/decoder.hh +++ b/src/arch/power/decoder.hh @@ -35,35 +35,19 @@ #include "arch/types.hh" #include "cpu/static_inst.hh" -class ThreadContext; - namespace PowerISA { class Decoder { protected: - ThreadContext * tc; - // The extended machine instruction being generated ExtMachInst emi; bool instDone; public: - Decoder(ThreadContext * _tc) : tc(_tc), instDone(false) - { - } - - ThreadContext * - getTC() - { - return tc; - } - - void - setTC(ThreadContext * _tc) + Decoder() : instDone(false) { - tc = _tc; } void diff --git a/src/arch/sparc/decoder.hh b/src/arch/sparc/decoder.hh index f85d5e4de..e7a806d81 100644 --- a/src/arch/sparc/decoder.hh +++ b/src/arch/sparc/decoder.hh @@ -35,9 +35,6 @@ #include "arch/sparc/registers.hh" #include "arch/types.hh" #include "cpu/static_inst.hh" -#include "cpu/thread_context.hh" - -class ThreadContext; namespace SparcISA { @@ -45,28 +42,15 @@ namespace SparcISA class Decoder { protected: - ThreadContext * tc; // The extended machine instruction being generated ExtMachInst emi; bool instDone; MiscReg asi; public: - Decoder(ThreadContext * _tc) : tc(_tc), instDone(false), asi(0) + Decoder() : instDone(false), asi(0) {} - ThreadContext * - getTC() - { - return tc; - } - - void - setTC(ThreadContext * _tc) - { - tc = _tc; - } - void process() {} void diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc index 4cfb93b0d..b8b4e88cc 100644 --- a/src/arch/sparc/isa.cc +++ b/src/arch/sparc/isa.cc @@ -29,6 +29,7 @@ */ #include "arch/sparc/asi.hh" +#include "arch/sparc/decoder.hh" #include "arch/sparc/isa.hh" #include "base/bitfield.hh" #include "base/trace.hh" @@ -550,7 +551,7 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc) switch (miscReg) { case MISCREG_ASI: - tc->getDecodePtr()->setContext(val); + tc->getDecoderPtr()->setContext(val); break; case MISCREG_STICK: case MISCREG_TICK: diff --git a/src/arch/x86/decoder.cc b/src/arch/x86/decoder.cc index 9dcb02902..f42fb28bf 100644 --- a/src/arch/x86/decoder.cc +++ b/src/arch/x86/decoder.cc @@ -33,7 +33,6 @@ #include "base/misc.hh" #include "base/trace.hh" #include "base/types.hh" -#include "cpu/thread_context.hh" #include "debug/Decoder.hh" namespace X86ISA diff --git a/src/arch/x86/decoder.hh b/src/arch/x86/decoder.hh index 796f9eef9..6f55ab26f 100644 --- a/src/arch/x86/decoder.hh +++ b/src/arch/x86/decoder.hh @@ -44,8 +44,6 @@ #include "cpu/static_inst.hh" #include "debug/Decoder.hh" -class ThreadContext; - namespace X86ISA { @@ -72,7 +70,6 @@ class Decoder static InstBytes dummy; - ThreadContext * tc; //The bytes to be predecoded MachInst fetchChunk; InstBytes *instBytes; @@ -205,8 +202,7 @@ class Decoder static InstCacheMap instCacheMap; public: - Decoder(ThreadContext * _tc) : - tc(_tc), basePC(0), origPC(0), offset(0), + Decoder() : basePC(0), origPC(0), offset(0), outOfBytes(true), instDone(false), state(ResetState) { @@ -259,16 +255,6 @@ class Decoder state = ResetState; } - ThreadContext * getTC() - { - return tc; - } - - void setTC(ThreadContext * _tc) - { - tc = _tc; - } - void process(); //Use this to give data to the decoder. This should be used |