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author | Korey Sewell <ksewell@umich.edu> | 2011-02-12 10:14:26 -0500 |
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committer | Korey Sewell <ksewell@umich.edu> | 2011-02-12 10:14:26 -0500 |
commit | e65c15e9316f47dfd3cb10786733eac7ac81822c (patch) | |
tree | 810dee0b01935d9d4818eb9cd0c63b4fd6150560 /src/arch | |
parent | 2055df8322f921f63852f445ff962c8c2503a646 (diff) | |
download | gem5-e65c15e9316f47dfd3cb10786733eac7ac81822c.tar.xz |
inorder: remove unused isa ops
pass/fail ops were used for testing but arent part of isa
Diffstat (limited to 'src/arch')
-rw-r--r-- | src/arch/mips/isa/decoder.isa | 16 |
1 files changed, 1 insertions, 15 deletions
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa index 173fa89df..d97a141de 100644 --- a/src/arch/mips/isa/decoder.isa +++ b/src/arch/mips/isa/decoder.isa @@ -367,21 +367,7 @@ decode OPCODE_HI default Unknown::unknown() { }}); 0x1: addiu({{ Rt.sw = Rs.sw + imm; }}); 0x2: slti({{ Rt.sw = (Rs.sw < imm) ? 1 : 0 }}); - - //Edited to include MIPS AVP Pass/Fail instructions and - //default to the sltiu instruction - 0x3: decode RS_RT_INTIMM { - 0xabc1: BasicOp::fail({{ - exitSimLoop("AVP/SRVP Test Failed"); - }}); - 0xabc2: BasicOp::pass({{ - exitSimLoop("AVP/SRVP Test Passed"); - }}); - default: sltiu({{ - Rt.uw = (Rs.uw < (uint32_t)sextImm) ? 1 : 0; - }}); - } - + 0x3: sltiu({{ Rt.uw = (Rs.uw < (uint32_t)sextImm) ? 1 : 0;}}); 0x4: andi({{ Rt.sw = Rs.sw & zextImm; }}); 0x5: ori({{ Rt.sw = Rs.sw | zextImm; }}); 0x6: xori({{ Rt.sw = Rs.sw ^ zextImm; }}); |