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authorGabe Black <gblack@eecs.umich.edu>2007-08-07 15:19:26 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-08-07 15:19:26 -0700
commitfb6cdf09cb4cfe9f39fdc7381168883fae6816ec (patch)
tree749d30835f7f27edbd21f913e057c9bc922eb528 /src/arch
parentcae8d20633c0f43fdae23576adfb894284a7ee86 (diff)
downloadgem5-fb6cdf09cb4cfe9f39fdc7381168883fae6816ec.tar.xz
X86: Make a microcode branch microop.
Also some touch up for ruflag. --HG-- extra : convert_revision : 829947169af25ca6573f53b9430707101c75cc23
Diffstat (limited to 'src/arch')
-rwxr-xr-xsrc/arch/isa_parser.py19
-rw-r--r--src/arch/x86/isa/microops/regop.isa5
-rw-r--r--src/arch/x86/isa/operands.isa4
3 files changed, 25 insertions, 3 deletions
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index 64a120c4c..fb398d152 100755
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -1464,6 +1464,25 @@ class MemOperand(Operand):
def makeAccSize(self):
return self.size
+class UPCOperand(Operand):
+ def makeConstructor(self):
+ return ''
+
+ def makeRead(self):
+ return '%s = xc->readMicroPC();\n' % self.base_name
+
+ def makeWrite(self):
+ return 'xc->setMicroPC(%s);\n' % self.base_name
+
+class NUPCOperand(Operand):
+ def makeConstructor(self):
+ return ''
+
+ def makeRead(self):
+ return '%s = xc->readNextMicroPC();\n' % self.base_name
+
+ def makeWrite(self):
+ return 'xc->setNextMicroPC(%s);\n' % self.base_name
class NPCOperand(Operand):
def makeConstructor(self):
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index ac88be657..c6a25279e 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -453,7 +453,7 @@ let {{
setUpMicroRegOp(name, Name, "X86ISA::RegOp", code);
- def defineMicroRegOpImm(mnemonic, code):
+ def defineMicroRegOpImm(mnemonic, code, flagCode=""):
Name = mnemonic
name = mnemonic.lower()
code = immPick + code
@@ -615,11 +615,12 @@ let {{
''')
defineMicroRegOpWr('Wrip', 'RIP = psrc1 + op2', elseCode="RIP = RIP;")
+ defineMicroRegOpWr('Br', 'nuIP = psrc1 + op2;', elseCode='nuIP = nuIP;')
defineMicroRegOpWr('Wruflags', 'ccFlagBits = psrc1 ^ op2')
defineMicroRegOpRd('Rdip', 'DestReg = RIP')
defineMicroRegOpRd('Ruflags', 'DestReg = ccFlagBits')
- defineMicroRegOpImm('Ruflag', 'DestReg = bits(ccFlagBits, imm8);', \
+ defineMicroRegOpImm('Ruflag', 'DestReg = bits(ccFlagBits, imm8 + 0*psrc1);', \
flagCode = genCCFlagBitsLogic)
defineMicroRegOpImm('Sext', '''
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index 64179ca98..098a75370 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -104,7 +104,9 @@ def operands {{
'Data': ('IntReg', 'uqw', '(((data & 0x1C) == 4 ? foldOBit : 0) | data)', 'IsInteger', 6),
'rax': ('IntReg', 'uqw', '(INTREG_RAX)', 'IsInteger', 7),
'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 10),
- 'ccFlagBits': ('IntReg', 'uqw', 'NUM_INTREGS + NumMicroIntRegs', None, 20),
+ 'uIP': ('UPC', 'uqw', None, (None, None, 'IsControl'), 11),
+ 'nuIP': ('NUPC', 'uqw', None, (None, None, 'IsControl'), 12),
+ 'ccFlagBits': ('IntReg', 'uqw', 'NUM_INTREGS + NumMicroIntRegs', None, 20),
'SegBase': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE_BASE + segment', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 50),
'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
}};