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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-03-27 14:23:28 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-04-06 09:58:41 +0000 |
| commit | 0fa5ed40c471429318c967833592aee0bd361dea (patch) | |
| tree | c532523a3f4bf4fec53d07d8f61190efa89255ac /src/arch | |
| parent | 906ef2f7cd043339ea917c9bf744210dc45999a9 (diff) | |
| download | gem5-0fa5ed40c471429318c967833592aee0bd361dea.tar.xz | |
arch-arm: Correct mcrr,mrrc disassemble
This patch is fixing AArch32 mcrr,mrrc instruction disassemble by
printing the correct source/destination registers
Change-Id: I3fcffa0349aeee466e7c60ba4d1244824fb65d91
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9501
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/arm/insts/misc.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc index 9c7a051f5..d4a2ba2d2 100644 --- a/src/arch/arm/insts/misc.cc +++ b/src/arch/arm/insts/misc.cc @@ -153,7 +153,7 @@ MrrcOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const ss << ", "; printIntReg(ss, dest2); ss << ", "; - printIntReg(ss, op1); + printMiscReg(ss, op1); return ss.str(); } @@ -162,7 +162,7 @@ McrrOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss); - printIntReg(ss, dest); + printMiscReg(ss, dest); ss << ", "; printIntReg(ss, op1); ss << ", "; |