syscall_emul: expand AuxVector class

The AuxVector class is responsible for holding Process data.
The data that it holds is normally setup by an OS kernel in
the process address space. The purpose behind doing this is
to pass in information that the process will need for various
reasons. (Check out the enum in the header file for an idea of
what the AuxVector holds.)

The AuxVector struct was changed into a class and encapsulation
methods were added to protect access to the member variables.

The host ISA may have a different endianness than the simulated
ISA. Since data is passed between the process address space and
the simulator for auxiliary vectors, we need to worry about
maintaining endianness for the right context.

Change-Id: I32c5ac4b679559886e1efeb4b5483b92dfc94af9
Reviewed-on: https://gem5-review.googlesource.com/12109
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

7 files changed, 36 insertions, 32 deletions

diff --git a/src/arch/alpha/process.cc b/src/arch/alpha/process.cc
index 112abbf4a..e8dad9917 100644
--- a/src/arch/alpha/process.cc
+++ b/src/arch/alpha/process.cc
@@ -170,9 +170,9 @@ AlphaProcess::argsInit(int intSize, int pageSize)
     //Copy the aux stuff
     for (vector<auxv_t>::size_type x = 0; x < auxv.size(); x++) {
         initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize,
-                (uint8_t*)&(auxv[x].a_type), intSize);
+                (uint8_t*)&(auxv[x].getAuxType()), intSize);
         initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
-                (uint8_t*)&(auxv[x].a_val), intSize);
+                (uint8_t*)&(auxv[x].getAuxVal()), intSize);
     }
 
     ThreadContext *tc = system->getThreadContext(contextIds[0]);
diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc
index 1bb23dec2..0c1d18bb1 100644
--- a/src/arch/arm/process.cc
+++ b/src/arch/arm/process.cc
@@ -346,14 +346,14 @@ ArmProcess::argsInit(int pageSize, IntRegIndex spIndex)
 
     //Fix up the aux vectors which point to other data
     for (int i = auxv.size() - 1; i >= 0; i--) {
-        if (auxv[i].a_type == M5_AT_PLATFORM) {
-            auxv[i].a_val = platform_base;
+        if (auxv[i].getHostAuxType() == M5_AT_PLATFORM) {
+            auxv[i].setAuxVal(platform_base);
             initVirtMem.writeString(platform_base, platform.c_str());
-        } else if (auxv[i].a_type == M5_AT_EXECFN) {
-            auxv[i].a_val = aux_data_base;
+        } else if (auxv[i].getHostAuxType() == M5_AT_EXECFN) {
+            auxv[i].setAuxVal(aux_data_base);
             initVirtMem.writeString(aux_data_base, filename.c_str());
-        } else if (auxv[i].a_type == M5_AT_RANDOM) {
-            auxv[i].a_val = aux_random_base;
+        } else if (auxv[i].getHostAuxType() == M5_AT_RANDOM) {
+            auxv[i].setAuxVal(aux_random_base);
             // Just leave the value 0, we don't want randomness
         }
     }
@@ -361,9 +361,11 @@ ArmProcess::argsInit(int pageSize, IntRegIndex spIndex)
     //Copy the aux stuff
     for (int x = 0; x < auxv.size(); x++) {
         initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize,
-                (uint8_t*)&(auxv[x].a_type), intSize);
+                              (uint8_t*)&(auxv[x].getAuxType()),
+                              intSize);
         initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
-                (uint8_t*)&(auxv[x].a_val), intSize);
+                              (uint8_t*)&(auxv[x].getAuxVal()),
+                              intSize);
     }
     //Write out the terminating zeroed auxilliary vector
     const uint64_t zero = 0;
diff --git a/src/arch/mips/process.cc b/src/arch/mips/process.cc
index b2957e0c4..3f65691aa 100644
--- a/src/arch/mips/process.cc
+++ b/src/arch/mips/process.cc
@@ -179,9 +179,9 @@ MipsProcess::argsInit(int pageSize)
     // Copy the aux vector
     for (typename vector<auxv_t>::size_type x = 0; x < auxv.size(); x++) {
         initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize,
-                (uint8_t*)&(auxv[x].a_type), intSize);
+                (uint8_t*)&(auxv[x].getAuxType()), intSize);
         initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
-                (uint8_t*)&(auxv[x].a_val), intSize);
+                (uint8_t*)&(auxv[x].getAuxVal()), intSize);
     }
 
     // Write out the terminating zeroed auxilliary vector
diff --git a/src/arch/power/process.cc b/src/arch/power/process.cc
index 6561bff4e..cf2153a1d 100644
--- a/src/arch/power/process.cc
+++ b/src/arch/power/process.cc
@@ -239,11 +239,11 @@ PowerProcess::argsInit(int intSize, int pageSize)
 
     //Fix up the aux vectors which point to other data
     for (int i = auxv.size() - 1; i >= 0; i--) {
-        if (auxv[i].a_type == M5_AT_PLATFORM) {
-            auxv[i].a_val = platform_base;
+        if (auxv[i].getHostAuxType() == M5_AT_PLATFORM) {
+            auxv[i].setAuxVal(platform_base);
             initVirtMem.writeString(platform_base, platform.c_str());
-        } else if (auxv[i].a_type == M5_AT_EXECFN) {
-            auxv[i].a_val = aux_data_base;
+        } else if (auxv[i].getHostAuxType() == M5_AT_EXECFN) {
+            auxv[i].setAuxVal(aux_data_base);
             initVirtMem.writeString(aux_data_base, filename.c_str());
         }
     }
@@ -252,9 +252,9 @@ PowerProcess::argsInit(int intSize, int pageSize)
     for (int x = 0; x < auxv.size(); x++)
     {
         initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize,
-                (uint8_t*)&(auxv[x].a_type), intSize);
+                (uint8_t*)&(auxv[x].getAuxType()), intSize);
         initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
-                (uint8_t*)&(auxv[x].a_val), intSize);
+                (uint8_t*)&(auxv[x].getAuxVal()), intSize);
     }
     //Write out the terminating zeroed auxilliary vector
     const uint64_t zero = 0;
diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index 4afc72147..4e97fcf42 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -205,11 +205,11 @@ RiscvProcess::argsInit(int pageSize)
     };
     for (const AuxVector<IntType>& aux: auxv) {
         DPRINTF(Stack, "Wrote aux key %s to address %p\n",
-                aux_keys[aux.a_type], (void*)sp);
-        pushOntoStack((uint8_t*)&aux.a_type, sizeof(IntType));
+                aux_keys[aux.getAuxType()], (void*)sp);
+        pushOntoStack((uint8_t*)&aux.getAuxType(), sizeof(IntType));
         DPRINTF(Stack, "Wrote aux value %x to address %p\n",
-                aux.a_val, (void*)sp);
-        pushOntoStack((uint8_t*)&aux.a_val, sizeof(IntType));
+                aux.getAuxVal(), (void*)sp);
+        pushOntoStack((uint8_t*)&aux.getAuxVal(), sizeof(IntType));
     }
 
     ThreadContext *tc = system->getThreadContext(contextIds[0]);
diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc
index e4cd874bd..7dda6ed21 100644
--- a/src/arch/sparc/process.cc
+++ b/src/arch/sparc/process.cc
@@ -375,9 +375,9 @@ SparcProcess::argsInit(int pageSize)
     // Copy the aux stuff
     for (int x = 0; x < auxv.size(); x++) {
         initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize,
-                (uint8_t*)&(auxv[x].a_type), intSize);
+                (uint8_t*)&(auxv[x].getAuxType()), intSize);
         initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
-                (uint8_t*)&(auxv[x].a_val), intSize);
+                (uint8_t*)&(auxv[x].getAuxVal()), intSize);
     }
 
     // Write out the terminating zeroed auxilliary vector
diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc
index 7c979c016..273e2c0f9 100644
--- a/src/arch/x86/process.cc
+++ b/src/arch/x86/process.cc
@@ -1000,20 +1000,22 @@ X86Process::argsInit(int pageSize,
     initVirtMem.writeString(file_name_base, filename.c_str());
 
     // Fix up the aux vectors which point to data
-    assert(auxv[auxv.size() - 3].a_type == M5_AT_RANDOM);
-    auxv[auxv.size() - 3].a_val = aux_data_base;
-    assert(auxv[auxv.size() - 2].a_type == M5_AT_EXECFN);
-    auxv[auxv.size() - 2].a_val = argv_array_base;
-    assert(auxv[auxv.size() - 1].a_type == M5_AT_PLATFORM);
-    auxv[auxv.size() - 1].a_val = aux_data_base + numRandomBytes;
+    assert(auxv[auxv.size() - 3].getHostAuxType() == M5_AT_RANDOM);
+    auxv[auxv.size() - 3].setAuxVal(aux_data_base);
+    assert(auxv[auxv.size() - 2].getHostAuxType() == M5_AT_EXECFN);
+    auxv[auxv.size() - 2].setAuxVal(argv_array_base);
+    assert(auxv[auxv.size() - 1].getHostAuxType() == M5_AT_PLATFORM);
+    auxv[auxv.size() - 1].setAuxVal(aux_data_base + numRandomBytes);
 
 
     // Copy the aux stuff
     for (int x = 0; x < auxv.size(); x++) {
         initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize,
-                (uint8_t*)&(auxv[x].a_type), intSize);
+                              (uint8_t*)&(auxv[x].getAuxType()),
+                              intSize);
         initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
-                (uint8_t*)&(auxv[x].a_val), intSize);
+                              (uint8_t*)&(auxv[x].getAuxVal()),
+                              intSize);
     }
     // Write out the terminating zeroed auxiliary vector
     const uint64_t zero = 0;