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| author | Lisa Hsu <hsul@eecs.umich.edu> | 2008-10-19 22:50:53 -0400 |
|---|---|---|
| committer | Lisa Hsu <hsul@eecs.umich.edu> | 2008-10-19 22:50:53 -0400 |
| commit | 4fac54f227f0ee0ee169955cb2510609434f7d85 (patch) | |
| tree | 1e2dd75286dc97032763217613a6e829d88852f6 /src/arch | |
| parent | 101c2d9174e34247c3f9013c24577a274a11ab39 (diff) | |
| parent | 9b8011e255ee419a689706704b92e5a816fd8d34 (diff) | |
| download | gem5-4fac54f227f0ee0ee169955cb2510609434f7d85.tar.xz | |
Automated merge with ssh://daystrom.m5sim.org//z/repo/m5
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/x86/interrupts.cc | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/arch/x86/interrupts.cc b/src/arch/x86/interrupts.cc index bbc651378..bfb4d5b9c 100644 --- a/src/arch/x86/interrupts.cc +++ b/src/arch/x86/interrupts.cc @@ -294,10 +294,9 @@ X86ISA::Interrupts::recvMessage(PacketPtr pkt) case 0: { TriggerIntMessage message = pkt->get<TriggerIntMessage>(); - uint8_t vector = message.vector; DPRINTF(LocalApic, "Got Trigger Interrupt message with vector %#x.\n", - vector); + message.vector); // Make sure we're really supposed to get this. assert((message.destMode == 0 && message.destination == id) || (bits((int)message.destination, id))); |