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authorGabe Black <gblack@eecs.umich.edu>2009-11-07 22:34:33 -0800
committerGabe Black <gblack@eecs.umich.edu>2009-11-07 22:34:33 -0800
commit18b21c1ecaf7858c592c56cf4c12ec8781f821ba (patch)
treeda54718af6cd1f78ca9203a495ef792085ac3bcc /src/arch
parent5cf2e7ccf027a485c2e2eb9a60b70c3b45853f0c (diff)
downloadgem5-18b21c1ecaf7858c592c56cf4c12ec8781f821ba.tar.xz
ARM: Get rid of some unneeded register indexes.
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm/registers.hh30
1 files changed, 0 insertions, 30 deletions
diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
index 7f9b6b828..07af32c1e 100644
--- a/src/arch/arm/registers.hh
+++ b/src/arch/arm/registers.hh
@@ -77,7 +77,6 @@ const int ReturnAddressReg = 14;
const int PCReg = 15;
const int ZeroReg = NumIntArchRegs;
-const int AddrReg = ZeroReg + 1; // Used to generate address for uops
const int SyscallNumReg = ReturnValueReg;
const int SyscallPseudoReturnReg = ReturnValueReg;
@@ -116,35 +115,6 @@ enum FCSRFields {
Cause_Field = 11
};
-enum MiscIntRegNums {
- zero_reg = NumIntArchRegs,
- addr_reg,
-
- rhi,
- rlo,
-
- r8_fiq, /* FIQ mode register bank */
- r9_fiq,
- r10_fiq,
- r11_fiq,
- r12_fiq,
-
- r13_fiq, /* FIQ mode SP and LR */
- r14_fiq,
-
- r13_irq, /* IRQ mode SP and LR */
- r14_irq,
-
- r13_svc, /* SVC mode SP and LR */
- r14_svc,
-
- r13_undef, /* UNDEF mode SP and LR */
- r14_undef,
-
- r13_abt, /* ABT mode SP and LR */
- r14_abt
-};
-
} // namespace ArmISA
#endif