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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-04-09 13:25:46 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-05-29 10:07:53 +0000 |
| commit | 2456c917ac654f6b67243c72a47240d22a2bf712 (patch) | |
| tree | b33944bd7588abe957d2acdf01e475db3133707d /src/arch | |
| parent | 6925bf55005c118dc2580ba83e0fa10b31839ef9 (diff) | |
| download | gem5-2456c917ac654f6b67243c72a47240d22a2bf712.tar.xz | |
arch-arm: Add E2H bit to HCR_EL2 System register
This patch adds the EL2 Host bit to the HCR_EL2 register. Enables a
configuration where a Host Operating System is running in EL2, and the
Host Operating System's applications are running in EL0.
Change-Id: I92d21ed9f8958c58f135dca1b6a97460ba4c02f9
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10381
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/arm/miscregs.hh | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index 06d1a0d79..b43b04f72 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -1478,6 +1478,7 @@ namespace ArmISA EndBitUnion(HSTR) BitUnion64(HCR) + Bitfield<34> e2h; // AArch64 Bitfield<33> id; // AArch64 Bitfield<32> cd; // AArch64 Bitfield<31> rw; // AArch64 |