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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:08 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:08 -0500
commit35f0c01fea89517530d11853eed513b4f2d5b497 (patch)
tree492c373e305222dc8122284153f3f636600935c5 /src/arch
parent7932b862986c325d647097e13ffb6a54a5cc93b9 (diff)
downloadgem5-35f0c01fea89517530d11853eed513b4f2d5b497.tar.xz
ARM: Decode the unimplemented cp15 instruction barrier.
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm/isa/formats/misc.isa3
-rw-r--r--src/arch/arm/miscregs.hh6
2 files changed, 6 insertions, 3 deletions
diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa
index 74e10a2d8..ace90786f 100644
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -101,6 +101,9 @@ def format McrMrc15() {{
case MISCREG_DCCIMVAC:
return new WarnUnimplemented(
isRead ? "mrc dccimvac" : "mcr dcimvac", machInst);
+ case MISCREG_CP15ISB:
+ return new WarnUnimplemented(
+ isRead ? "mrc cp15isb" : "mcr cp15isb", machInst);
default:
if (isRead) {
return new Mrc15(machInst, rt, (IntRegIndex)miscReg);
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index c1c7e9422..bdb98a6ff 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -88,6 +88,7 @@ namespace ArmISA
MISCREG_TPIDRURW,
MISCREG_TPIDRURO,
MISCREG_TPIDRPRW,
+ MISCREG_CP15ISB,
MISCREG_CP15_UNIMP_START,
MISCREG_CTR = MISCREG_CP15_UNIMP_START,
MISCREG_TCMTR,
@@ -131,7 +132,6 @@ namespace ArmISA
MISCREG_BPIALLIS,
MISCREG_ICIALLU,
MISCREG_ICIMVAU,
- MISCREG_CP15ISB,
MISCREG_BPIALL,
MISCREG_BPIMVA,
MISCREG_DCIMVAC,
@@ -160,7 +160,7 @@ namespace ArmISA
"fpsr", "fpsid", "fpscr", "fpexc",
"sctlr", "dccisw", "dccimvac",
"contextidr", "tpidrurw", "tpidruro", "tpidrprw",
- "ctr", "tcmtr", "mpuir", "mpidr", "midr",
+ "cp15isb", "ctr", "tcmtr", "mpuir", "mpidr", "midr",
"id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
"id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
"id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
@@ -168,7 +168,7 @@ namespace ArmISA
"dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
"drbar", "irbar", "drsr", "irsr", "dracr", "iracr",
"rgnr", "icialluis", "bpiallis", "iciallu", "icimvau",
- "cp15isb", "bpiall", "bpimva", "dcimvac", "dcisw", "dccmvac", "mccsw",
+ "bpiall", "bpimva", "dcimvac", "dcisw", "dccmvac", "mccsw",
"cp15dsb", "cp15dmb", "dccmvau",
"nop", "raz"
};