CPU: Separate out native trace into ISA (in)dependent code and SimObjects.

--HG--
rename : src/cpu/nativetrace.cc => src/arch/sparc/nativetrace.cc
rename : src/cpu/nativetrace.hh => src/arch/sparc/nativetrace.hh
rename : src/cpu/NativeTrace.py => src/arch/x86/X86NativeTrace.py

8 files changed, 514 insertions, 0 deletions

diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript
index 86ccaa010..b59e9ea7a 100644
--- a/src/arch/sparc/SConscript
+++ b/src/arch/sparc/SConscript
@@ -35,11 +35,14 @@ if env['TARGET_ISA'] == 'sparc':
     Source('asi.cc')
     Source('faults.cc')
     Source('isa.cc')
+    Source('nativetrace.cc')
     Source('pagetable.cc')
     Source('remote_gdb.cc')
     Source('tlb.cc')
     Source('utility.cc')
 
+    SimObject('SparcNativeTrace.py')
+
     SimObject('SparcTLB.py')
     TraceFlag('Sparc', "Generic SPARC ISA stuff")
     TraceFlag('RegisterWindows', "Register window manipulation")
diff --git a/src/arch/sparc/SparcNativeTrace.py b/src/arch/sparc/SparcNativeTrace.py
new file mode 100644
index 000000000..0a92764ef
--- /dev/null
+++ b/src/arch/sparc/SparcNativeTrace.py
@@ -0,0 +1,35 @@
+# Copyright (c) 2009 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+from m5.SimObject import SimObject
+from m5.params import *
+from NativeTrace import NativeTrace
+
+class SparcNativeTrace(NativeTrace):
+    type = 'SparcNativeTrace'
+    cxx_class = 'Trace::SparcNativeTrace'
diff --git a/src/arch/sparc/nativetrace.cc b/src/arch/sparc/nativetrace.cc
new file mode 100644
index 000000000..6e894e8df
--- /dev/null
+++ b/src/arch/sparc/nativetrace.cc
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/sparc/isa_traits.hh"
+#include "arch/sparc/registers.hh"
+#include "arch/sparc/nativetrace.hh"
+#include "cpu/thread_context.hh"
+#include "params/SparcNativeTrace.hh"
+
+namespace Trace {
+
+static char *intRegNames[SparcISA::NumIntArchRegs] = {
+    //Global registers
+    "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
+    //Output registers
+    "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7",
+    //Local registers
+    "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
+    //Input registers
+    "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
+};
+
+void
+Trace::SparcNativeTrace::check(NativeTraceRecord *record)
+{
+    ThreadContext *tc = record->getThread();
+
+    uint64_t regVal, realRegVal;
+
+    // Integer registers
+
+    // I doubt a real SPARC will describe more integer registers than this.
+    assert(SparcISA::NumIntArchRegs == 32);
+    char **regName = intRegNames;
+    for (int i = 0; i < SparcISA::NumIntArchRegs; i++) {
+        regVal = tc->readIntReg(i);
+        read(&realRegVal, sizeof(realRegVal));
+        realRegVal = SparcISA::gtoh(realRegVal);
+        checkReg(*(regName++), regVal, realRegVal);
+    }
+
+    // PC
+    read(&realRegVal, sizeof(realRegVal));
+    realRegVal = SparcISA::gtoh(realRegVal);
+    regVal = tc->readNextPC();
+    checkReg("pc", regVal, realRegVal);
+
+    // NPC
+    read(&realRegVal, sizeof(realRegVal));
+    realRegVal = SparcISA::gtoh(realRegVal);
+    regVal = tc->readNextNPC();
+    checkReg("npc", regVal, realRegVal);
+
+    // CCR
+    read(&realRegVal, sizeof(realRegVal));
+    realRegVal = SparcISA::gtoh(realRegVal);
+    regVal = tc->readIntReg(SparcISA::NumIntArchRegs + 2);
+    checkReg("ccr", regVal, realRegVal);
+}
+
+} /* namespace Trace */
+
+////////////////////////////////////////////////////////////////////////
+//
+//  ExeTracer Simulation Object
+//
+Trace::SparcNativeTrace *
+SparcNativeTraceParams::create()
+{
+    return new Trace::SparcNativeTrace(this);
+};
diff --git a/src/arch/sparc/nativetrace.hh b/src/arch/sparc/nativetrace.hh
new file mode 100644
index 000000000..d618107bb
--- /dev/null
+++ b/src/arch/sparc/nativetrace.hh
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_SPARC_NATIVETRACE_HH__
+#define __ARCH_SPARC_NATIVETRACE_HH__
+
+#include "base/types.hh"
+#include "cpu/nativetrace.hh"
+
+class ThreadContext;
+
+namespace Trace {
+
+class SparcNativeTrace : public NativeTrace
+{
+  public:
+    SparcNativeTrace(const Params *p) : NativeTrace(p)
+    {}
+
+    void check(NativeTraceRecord *record);
+};
+
+} /* namespace Trace */
+
+#endif // __CPU_NATIVETRACE_HH__
diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript
index 96af0767c..3d1f6f8e3 100644
--- a/src/arch/x86/SConscript
+++ b/src/arch/x86/SConscript
@@ -95,6 +95,7 @@ if env['TARGET_ISA'] == 'x86':
     Source('insts/microregop.cc')
     Source('insts/static_inst.cc')
     Source('isa.cc')
+    Source('nativetrace.cc')
     Source('pagetable.cc')
     Source('predecoder.cc')
     Source('predecoder_tables.cc')
@@ -102,6 +103,8 @@ if env['TARGET_ISA'] == 'x86':
     Source('tlb.cc')
     Source('utility.cc')
 
+    SimObject('X86NativeTrace.py')
+
     SimObject('X86TLB.py')
     TraceFlag('Predecoder', "Predecoder debug output")
     TraceFlag('X86', "Generic X86 ISA debugging")
diff --git a/src/arch/x86/X86NativeTrace.py b/src/arch/x86/X86NativeTrace.py
new file mode 100644
index 000000000..cbed77f37
--- /dev/null
+++ b/src/arch/x86/X86NativeTrace.py
@@ -0,0 +1,35 @@
+# Copyright (c) 2009 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+from m5.SimObject import SimObject
+from m5.params import *
+from NativeTrace import NativeTrace
+
+class X86NativeTrace(NativeTrace):
+    type = 'X86NativeTrace'
+    cxx_class = 'Trace::X86NativeTrace'
diff --git a/src/arch/x86/nativetrace.cc b/src/arch/x86/nativetrace.cc
new file mode 100644
index 000000000..1ce7505ad
--- /dev/null
+++ b/src/arch/x86/nativetrace.cc
@@ -0,0 +1,198 @@
+/*
+ * Copyright (c) 2007-2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/x86/isa_traits.hh"
+#include "arch/x86/floatregs.hh"
+#include "arch/x86/intregs.hh"
+#include "arch/x86/nativetrace.hh"
+#include "cpu/thread_context.hh"
+#include "params/X86NativeTrace.hh"
+
+namespace Trace {
+
+void
+X86NativeTrace::ThreadState::update(NativeTrace *parent)
+{
+    parent->read(this, sizeof(*this));
+    rax = X86ISA::gtoh(rax);
+    rcx = X86ISA::gtoh(rcx);
+    rdx = X86ISA::gtoh(rdx);
+    rbx = X86ISA::gtoh(rbx);
+    rsp = X86ISA::gtoh(rsp);
+    rbp = X86ISA::gtoh(rbp);
+    rsi = X86ISA::gtoh(rsi);
+    rdi = X86ISA::gtoh(rdi);
+    r8 = X86ISA::gtoh(r8);
+    r9 = X86ISA::gtoh(r9);
+    r10 = X86ISA::gtoh(r10);
+    r11 = X86ISA::gtoh(r11);
+    r12 = X86ISA::gtoh(r12);
+    r13 = X86ISA::gtoh(r13);
+    r14 = X86ISA::gtoh(r14);
+    r15 = X86ISA::gtoh(r15);
+    rip = X86ISA::gtoh(rip);
+    //This should be expanded if x87 registers are considered
+    for (int i = 0; i < 8; i++)
+        mmx[i] = X86ISA::gtoh(mmx[i]);
+    for (int i = 0; i < 32; i++)
+        xmm[i] = X86ISA::gtoh(xmm[i]);
+}
+
+void
+X86NativeTrace::ThreadState::update(ThreadContext *tc)
+{
+    rax = tc->readIntReg(X86ISA::INTREG_RAX);
+    rcx = tc->readIntReg(X86ISA::INTREG_RCX);
+    rdx = tc->readIntReg(X86ISA::INTREG_RDX);
+    rbx = tc->readIntReg(X86ISA::INTREG_RBX);
+    rsp = tc->readIntReg(X86ISA::INTREG_RSP);
+    rbp = tc->readIntReg(X86ISA::INTREG_RBP);
+    rsi = tc->readIntReg(X86ISA::INTREG_RSI);
+    rdi = tc->readIntReg(X86ISA::INTREG_RDI);
+    r8 = tc->readIntReg(X86ISA::INTREG_R8);
+    r9 = tc->readIntReg(X86ISA::INTREG_R9);
+    r10 = tc->readIntReg(X86ISA::INTREG_R10);
+    r11 = tc->readIntReg(X86ISA::INTREG_R11);
+    r12 = tc->readIntReg(X86ISA::INTREG_R12);
+    r13 = tc->readIntReg(X86ISA::INTREG_R13);
+    r14 = tc->readIntReg(X86ISA::INTREG_R14);
+    r15 = tc->readIntReg(X86ISA::INTREG_R15);
+    rip = tc->readNextPC();
+    //This should be expanded if x87 registers are considered
+    for (int i = 0; i < 8; i++)
+        mmx[i] = tc->readFloatRegBits(X86ISA::FLOATREG_MMX(i));
+    for (int i = 0; i < 32; i++)
+        xmm[i] = tc->readFloatRegBits(X86ISA::FLOATREG_XMM_BASE + i);
+}
+
+
+X86NativeTrace::X86NativeTrace(const Params *p)
+    : NativeTrace(p)
+{
+    checkRcx = true;
+    checkR11 = true;
+}
+
+bool
+X86NativeTrace::checkRcxReg(const char * name, uint64_t &mVal, uint64_t &nVal)
+{
+    if(!checkRcx)
+        checkRcx = (mVal != oldRcxVal || nVal != oldRealRcxVal);
+    if(checkRcx)
+        return checkReg(name, mVal, nVal);
+    return true;
+}
+
+bool
+X86NativeTrace::checkR11Reg(const char * name, uint64_t &mVal, uint64_t &nVal)
+{
+    if(!checkR11)
+        checkR11 = (mVal != oldR11Val || nVal != oldRealR11Val);
+    if(checkR11)
+        return checkReg(name, mVal, nVal);
+    return true;
+}
+
+bool
+X86NativeTrace::checkXMM(int num, uint64_t mXmmBuf[], uint64_t nXmmBuf[])
+{
+    if (mXmmBuf[num * 2]     != nXmmBuf[num * 2] ||
+        mXmmBuf[num * 2 + 1] != nXmmBuf[num * 2 + 1]) {
+        DPRINTF(ExecRegDelta,
+                "Register xmm%d should be 0x%016x%016x but is 0x%016x%016x.\n",
+                num, nXmmBuf[num * 2 + 1], nXmmBuf[num * 2],
+                     mXmmBuf[num * 2 + 1], mXmmBuf[num * 2]);
+        return false;
+    }
+    return true;
+}
+
+void
+X86NativeTrace::check(NativeTraceRecord *record)
+{
+    nState.update(this);
+    mState.update(record->getThread());
+
+    if(record->getStaticInst()->isSyscall())
+    {
+        checkRcx = false;
+        checkR11 = false;
+        oldRcxVal = mState.rcx;
+        oldRealRcxVal = nState.rcx;
+        oldR11Val = mState.r11;
+        oldRealR11Val = nState.r11;
+    }
+
+    checkReg("rax", mState.rax, nState.rax);
+    checkRcxReg("rcx", mState.rcx, nState.rcx);
+    checkReg("rdx", mState.rdx, nState.rdx);
+    checkReg("rbx", mState.rbx, nState.rbx);
+    checkReg("rsp", mState.rsp, nState.rsp);
+    checkReg("rbp", mState.rbp, nState.rbp);
+    checkReg("rsi", mState.rsi, nState.rsi);
+    checkReg("rdi", mState.rdi, nState.rdi);
+    checkReg("r8",  mState.r8,  nState.r8);
+    checkReg("r9",  mState.r9,  nState.r9);
+    checkReg("r10", mState.r10, nState.r10);
+    checkR11Reg("r11", mState.r11, nState.r11);
+    checkReg("r12", mState.r12, nState.r12);
+    checkReg("r13", mState.r13, nState.r13);
+    checkReg("r14", mState.r14, nState.r14);
+    checkReg("r15", mState.r15, nState.r15);
+    checkReg("rip", mState.rip, nState.rip);
+    checkXMM(0, mState.xmm, nState.xmm);
+    checkXMM(1, mState.xmm, nState.xmm);
+    checkXMM(2, mState.xmm, nState.xmm);
+    checkXMM(3, mState.xmm, nState.xmm);
+    checkXMM(4, mState.xmm, nState.xmm);
+    checkXMM(5, mState.xmm, nState.xmm);
+    checkXMM(6, mState.xmm, nState.xmm);
+    checkXMM(7, mState.xmm, nState.xmm);
+    checkXMM(8, mState.xmm, nState.xmm);
+    checkXMM(9, mState.xmm, nState.xmm);
+    checkXMM(10, mState.xmm, nState.xmm);
+    checkXMM(11, mState.xmm, nState.xmm);
+    checkXMM(12, mState.xmm, nState.xmm);
+    checkXMM(13, mState.xmm, nState.xmm);
+    checkXMM(14, mState.xmm, nState.xmm);
+    checkXMM(15, mState.xmm, nState.xmm);
+}
+
+} /* namespace Trace */
+
+////////////////////////////////////////////////////////////////////////
+//
+//  ExeTracer Simulation Object
+//
+Trace::X86NativeTrace *
+X86NativeTraceParams::create()
+{
+    return new Trace::X86NativeTrace(this);
+};
diff --git a/src/arch/x86/nativetrace.hh b/src/arch/x86/nativetrace.hh
new file mode 100644
index 000000000..afa2a463d
--- /dev/null
+++ b/src/arch/x86/nativetrace.hh
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2007-2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_X86_NATIVETRACE_HH__
+#define __ARCH_X86_NATIVETRACE_HH__
+
+#include "base/types.hh"
+#include "cpu/nativetrace.hh"
+
+class ThreadContext;
+
+namespace Trace {
+
+class X86NativeTrace : public NativeTrace
+{
+  protected:
+    bool checkRcx;
+    bool checkR11;
+    uint64_t oldRcxVal, oldR11Val;
+    uint64_t oldRealRcxVal, oldRealR11Val;
+
+    struct ThreadState {
+        uint64_t rax;
+        uint64_t rcx;
+        uint64_t rdx;
+        uint64_t rbx;
+        uint64_t rsp;
+        uint64_t rbp;
+        uint64_t rsi;
+        uint64_t rdi;
+        uint64_t r8;
+        uint64_t r9;
+        uint64_t r10;
+        uint64_t r11;
+        uint64_t r12;
+        uint64_t r13;
+        uint64_t r14;
+        uint64_t r15;
+        uint64_t rip;
+        //This should be expanded to 16 if x87 registers are considered
+        uint64_t mmx[8];
+        uint64_t xmm[32];
+
+        void update(NativeTrace *parent);
+        void update(ThreadContext *tc);
+    };
+
+    ThreadState nState;
+    ThreadState mState;
+
+    bool checkRcxReg(const char * regName, uint64_t &, uint64_t &);
+    bool checkR11Reg(const char * regName, uint64_t &, uint64_t &);
+    bool checkXMM(int num, uint64_t mXmmBuf[], uint64_t nXmmBuf[]);
+
+  public:
+    X86NativeTrace(const Params *p);
+
+    void check(NativeTraceRecord *record);
+};
+
+} /* namespace Trace */
+
+#endif // __ARCH_X86_NATIVETRACE_HH__