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| author | Gabe Black <gblack@eecs.umich.edu> | 2006-11-03 14:42:12 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-11-03 14:42:12 -0500 |
| commit | 601822c6b507f6c3145eacf8f9db216522f70733 (patch) | |
| tree | 41724a5c8b58b751f9487488a64758216d799880 /src/arch | |
| parent | 8778d85b2d352fdbfbbf077332790f94852b20d3 (diff) | |
| download | gem5-601822c6b507f6c3145eacf8f9db216522f70733.tar.xz | |
Make things compile in SE again.
--HG--
extra : convert_revision : cf7faf5001b31d61c61ddce2386d61c919075800
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/sparc/miscregfile.cc | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc index a66e40717..217fba0bd 100644 --- a/src/arch/sparc/miscregfile.cc +++ b/src/arch/sparc/miscregfile.cc @@ -322,8 +322,8 @@ void MiscRegFile::setRegWithEffect(int miscReg, const MiscReg &val, ThreadContext * tc) { const uint64_t Bit64 = (1ULL << 63); - uint64_t time; #if FULL_SYSTEM + uint64_t time; SparcSystem *sys; #endif switch (miscReg) { @@ -364,6 +364,7 @@ void MiscRegFile::setRegWithEffect(int miscReg, case MISCREG_SOFTINT_SET: //Do whatever this is supposed to do... break; +#if FULL_SYSTEM case MISCREG_TICK_CMPR: if (tickCompare == NULL) tickCompare = new TickCompareEvent(this, tc); @@ -374,6 +375,7 @@ void MiscRegFile::setRegWithEffect(int miscReg, if (!tick_cmprFields.int_dis && time > 0) tickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); break; +#endif case MISCREG_PIL: //We need to inject interrupts, and or notify the interrupt //object that it needs to use a different interrupt level. @@ -482,6 +484,7 @@ void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section) implicitDataAsi = (ASI)temp; } +#if FULL_SYSTEM void MiscRegFile::processTickCompare(ThreadContext *tc) { @@ -499,3 +502,4 @@ MiscRegFile::processHSTickCompare(ThreadContext *tc) { panic("tick compare not implemented\n"); } +#endif |