CPU: Implement translateTiming which defers to translateAtomic, and convert the timing simple CPU to use it.

8 files changed, 101 insertions, 18 deletions

diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index 82d410987..2b0afacfe 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -317,7 +317,7 @@ ITB::regStats()
 }
 
 Fault
-ITB::translateAtomic(RequestPtr &req, ThreadContext *tc)
+ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
 {
     //If this is a pal pc, then set PHYSICAL
     if (FULL_SYSTEM && PcPAL(req->getPC()))
@@ -401,6 +401,14 @@ ITB::translateAtomic(RequestPtr &req, ThreadContext *tc)
 
 }
 
+void
+ITB::translateTiming(RequestPtr req, ThreadContext *tc,
+        Translation *translation)
+{
+    assert(translation);
+    translation->finish(translateAtomic(req, tc), req, tc, false);
+}
+
 ///////////////////////////////////////////////////////////////////////
 //
 //  Alpha DTB
@@ -479,7 +487,7 @@ DTB::regStats()
 }
 
 Fault
-DTB::translateAtomic(RequestPtr &req, ThreadContext *tc, bool write)
+DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write)
 {
     Addr pc = tc->readPC();
 
@@ -616,6 +624,14 @@ DTB::translateAtomic(RequestPtr &req, ThreadContext *tc, bool write)
     return checkCacheability(req);
 }
 
+void
+DTB::translateTiming(RequestPtr req, ThreadContext *tc,
+        Translation *translation, bool write)
+{
+    assert(translation);
+    translation->finish(translateAtomic(req, tc, write), req, tc, write);
+}
+
 TlbEntry &
 TLB::index(bool advance)
 {
diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh
index f5d2dbca9..877533797 100644
--- a/src/arch/alpha/tlb.hh
+++ b/src/arch/alpha/tlb.hh
@@ -131,7 +131,9 @@ class ITB : public TLB
     ITB(const Params *p);
     virtual void regStats();
 
-    Fault translateAtomic(RequestPtr &req, ThreadContext *tc);
+    Fault translateAtomic(RequestPtr req, ThreadContext *tc);
+    void translateTiming(RequestPtr req, ThreadContext *tc,
+            Translation *translation);
 };
 
 class DTB : public TLB
@@ -155,7 +157,9 @@ class DTB : public TLB
     DTB(const Params *p);
     virtual void regStats();
 
-    Fault translateAtomic(RequestPtr &req, ThreadContext *tc, bool write);
+    Fault translateAtomic(RequestPtr req, ThreadContext *tc, bool write);
+    void translateTiming(RequestPtr req, ThreadContext *tc,
+            Translation *translation, bool write);
 };
 
 } // namespace AlphaISA
diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc
index db21c7919..eac44eba8 100644
--- a/src/arch/mips/tlb.cc
+++ b/src/arch/mips/tlb.cc
@@ -310,7 +310,7 @@ TLB::regStats()
 }
 
 Fault
-ITB::translateAtomic(RequestPtr &req, ThreadContext *tc)
+ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
 {
 #if !FULL_SYSTEM
     Process * p = tc->getProcessPtr();
@@ -426,8 +426,16 @@ ITB::translateAtomic(RequestPtr &req, ThreadContext *tc)
 #endif
 }
 
+void
+ITB::translateTiming(RequestPtr req, ThreadContext *tc,
+        Translation *translation)
+{
+    assert(translation);
+    translation->finish(translateAtomic(req, tc), req, tc, false);
+}
+
 Fault
-DTB::translateAtomic(RequestPtr &req, ThreadContext *tc, bool write)
+DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write)
 {
 #if !FULL_SYSTEM
     Process * p = tc->getProcessPtr();
@@ -564,6 +572,14 @@ DTB::translateAtomic(RequestPtr &req, ThreadContext *tc, bool write)
 #endif
 }
 
+void
+DTB::translateTiming(RequestPtr req, ThreadContext *tc,
+        Translation *translation, bool write)
+{
+    assert(translation);
+    translation->finish(translateAtomic(req, tc, write), req, tc, write);
+}
+
 ///////////////////////////////////////////////////////////////////////
 //
 //  Mips ITB
diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
index acb393116..1ab9d77e5 100644
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -145,7 +145,9 @@ class ITB : public TLB {
     typedef MipsTLBParams Params;
     ITB(const Params *p);
 
-    Fault translateAtomic(RequestPtr &req, ThreadContext *tc);
+    Fault translateAtomic(RequestPtr req, ThreadContext *tc);
+    void translateTiming(RequestPtr req, ThreadContext *tc,
+            Translation *translation);
 };
 
 class DTB : public TLB {
@@ -153,8 +155,10 @@ class DTB : public TLB {
     typedef MipsTLBParams Params;
     DTB(const Params *p);
 
-    Fault translateAtomic(RequestPtr &req, ThreadContext *tc,
+    Fault translateAtomic(RequestPtr req, ThreadContext *tc,
             bool write = false);
+    void translateTiming(RequestPtr req, ThreadContext *tc,
+            Translation *translation, bool write = false);
 };
 
 class UTB : public ITB, public DTB {
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 683d916df..95ad0229e 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -436,7 +436,7 @@ DTB::writeSfsr(Addr a, bool write, ContextType ct,
 }
 
 Fault
-ITB::translateAtomic(RequestPtr &req, ThreadContext *tc)
+ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
 {
     uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
 
@@ -548,8 +548,16 @@ ITB::translateAtomic(RequestPtr &req, ThreadContext *tc)
     return NoFault;
 }
 
+void
+ITB::translateTiming(RequestPtr req, ThreadContext *tc,
+        Translation *translation)
+{
+    assert(translation);
+    translation->finish(translateAtomic(req, tc), req, tc, false);
+}
+
 Fault
-DTB::translateAtomic(RequestPtr &req, ThreadContext *tc, bool write)
+DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write)
 {
     /*
      * @todo this could really use some profiling and fixing to make
@@ -847,6 +855,14 @@ handleMmuRegAccess:
     return NoFault;
 };
 
+void
+DTB::translateTiming(RequestPtr req, ThreadContext *tc,
+        Translation *translation, bool write)
+{
+    assert(translation);
+    translation->finish(translateAtomic(req, tc, write), req, tc, write);
+}
+
 #if FULL_SYSTEM
 
 Tick
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index d563772e6..4fe532d4a 100644
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -177,7 +177,9 @@ class ITB : public TLB
         cacheEntry = NULL;
     }
 
-    Fault translateAtomic(RequestPtr &req, ThreadContext *tc);
+    Fault translateAtomic(RequestPtr req, ThreadContext *tc);
+    void translateTiming(RequestPtr req, ThreadContext *tc,
+            Translation *translation);
   private:
     void writeSfsr(bool write, ContextType ct,
             bool se, FaultTypes ft, int asi);
@@ -199,7 +201,10 @@ class DTB : public TLB
         cacheEntry[1] = NULL;
     }
 
-    Fault translateAtomic(RequestPtr &req, ThreadContext *tc, bool write);
+    Fault translateAtomic(RequestPtr req,
+            ThreadContext *tc, bool write=false);
+    void translateTiming(RequestPtr req, ThreadContext *tc,
+            Translation *translation, bool write=false);
 #if FULL_SYSTEM
     Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
     Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 33017a6aa..a34922b44 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -190,7 +190,7 @@ TLB::demapPage(Addr va, uint64_t asn)
 
 template<class TlbFault>
 Fault
-TLB::translateAtomic(RequestPtr &req, ThreadContext *tc,
+TLB::translateAtomic(RequestPtr req, ThreadContext *tc,
         bool write, bool execute)
 {
     Addr vaddr = req->getVaddr();
@@ -663,17 +663,33 @@ TLB::translateAtomic(RequestPtr &req, ThreadContext *tc,
 };
 
 Fault
-DTB::translateAtomic(RequestPtr &req, ThreadContext *tc, bool write)
+DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write)
 {
     return TLB::translateAtomic<FakeDTLBFault>(req, tc, write, false);
 }
 
+void
+DTB::translateTiming(RequestPtr req, ThreadContext *tc,
+        Translation *translation, bool write)
+{
+    assert(translation);
+    translation->finish(translateAtomic(req, tc, write), req, tc, write);
+}
+
 Fault
-ITB::translateAtomic(RequestPtr &req, ThreadContext *tc)
+ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
 {
     return TLB::translateAtomic<FakeITLBFault>(req, tc, false, true);
 }
 
+void
+ITB::translateTiming(RequestPtr req, ThreadContext *tc,
+        Translation *translation)
+{
+    assert(translation);
+    translation->finish(translateAtomic(req, tc), req, tc, false);
+}
+
 #if FULL_SYSTEM
 
 Tick
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index 91bb4a761..56730983a 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -138,8 +138,10 @@ namespace X86ISA
         EntryList entryList;
 
         template<class TlbFault>
-        Fault translateAtomic(RequestPtr &req, ThreadContext *tc,
+        Fault translateAtomic(RequestPtr req, ThreadContext *tc,
                 bool write, bool execute);
+        void translateTiming(RequestPtr req, ThreadContext *tc,
+                Translation *translation, bool write, bool execute);
 
       public:
 
@@ -159,7 +161,9 @@ namespace X86ISA
             _allowNX = false;
         }
 
-        Fault translateAtomic(RequestPtr &req, ThreadContext *tc);
+        Fault translateAtomic(RequestPtr req, ThreadContext *tc);
+        void translateTiming(RequestPtr req, ThreadContext *tc,
+                Translation *translation);
 
         friend class DTB;
     };
@@ -172,7 +176,9 @@ namespace X86ISA
         {
             _allowNX = true;
         }
-        Fault translateAtomic(RequestPtr &req, ThreadContext *tc, bool write);
+        Fault translateAtomic(RequestPtr req, ThreadContext *tc, bool write);
+        void translateTiming(RequestPtr req, ThreadContext *tc,
+                Translation *translation, bool write);
 #if FULL_SYSTEM
         Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
         Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);