next round of MIPS ISA changes

src/arch/mips/isa/decoder.isa:
    div,divu,ext,seb,seh, fp conditonal moves, fp indexed memory...
src/arch/mips/isa/formats/mem.isa:
    MemoryNoDisp class .. use sext<> function instead of doing it manually
src/arch/mips/regfile/float_regfile.hh:
    use bits function

--HG--
extra : convert_revision : cbbda9499185b91bdb2a6198fe1b961be04f9265

3 files changed, 61 insertions, 35 deletions

diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index a64f74c4f..14aa0cc77 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -158,14 +158,16 @@ decode OPCODE_HI default Unknown::unknown() {
                 }
 
                 format HiLoMiscOp {
-                    0x2: div({{
-                        HI = Rs.sd % Rt.sd;
-                        LO = Rs.sd / Rt.sd;
-                    }});
-                    0x3: divu({{
-                        HI = Rs.ud % Rt.ud;
-                        LO = Rs.ud / Rt.ud;
-                    }});
+                    0x2: div({{ if (Rt.sd != 0) {
+                                    HI = Rs.sd % Rt.sd;
+                                    LO = Rs.sd / Rt.sd;
+                                }
+                             }});
+                    0x3: divu({{ if (Rt.ud != 0) {
+                                     HI = Rs.ud % Rt.ud;
+                                     LO = Rs.ud / Rt.ud;
+                                 }
+                              }});
                 }
             }
 
@@ -333,7 +335,7 @@ decode OPCODE_HI default Unknown::unknown() {
             0x0: decode RS_HI {
                 0x0: decode RS_LO {
                     format CP1Control {
-                        0x0: mfc1 ({{ Rt.uw = Fs.uw<31:0>; }});
+                        0x0: mfc1 ({{ Rt.uw = Fs.uw; }});
 
                         0x2: cfc1({{
                             switch (FS)
@@ -438,9 +440,10 @@ decode OPCODE_HI default Unknown::unknown() {
                                 0x3: div_s({{ Fd.sf = Fs.sf / Ft.sf;}});
                                 0x4: sqrt_s({{ Fd.sf = sqrt(Fs.sf);}});
                                 0x5: abs_s({{ Fd.sf = fabs(Fs.sf);}});
-                                0x6: mov_s({{ Fd.sf = Fs.sf;}});
                                 0x7: neg_s({{ Fd.sf = -Fs.sf;}});
                             }
+
+                            0x6: BasicOp::mov_s({{ Fd.sf = Fs.sf;}});
                         }
 
                         0x1: decode FUNCTION_LO {
@@ -549,9 +552,10 @@ decode OPCODE_HI default Unknown::unknown() {
                                 0x3: div_d({{ Fd.df = Fs.df / Ft.df; }});
                                 0x4: sqrt_d({{ Fd.df = sqrt(Fs.df);  }});
                                 0x5: abs_d({{ Fd.df = fabs(Fs.df);   }});
-                                0x6: mov_d({{ Fd.df = Fs.df;         }});
                                 0x7: neg_d({{ Fd.df = -1 * Fs.df;    }});
                             }
+
+                            0x6: BasicOp::mov_d({{ Fd.df = Fs.df;    }});
                         }
 
                         0x1: decode FUNCTION_LO {
@@ -853,17 +857,19 @@ decode OPCODE_HI default Unknown::unknown() {
         0x3: decode FUNCTION_HI {
             0x0: decode FUNCTION_LO {
                 format LoadIndexedMemory {
-                    0x0: lwxc1({{ Ft.uw = Mem.uw;}});
-                    0x1: ldxc1({{ Ft.ud = Mem.ud;}});
-                    0x5: luxc1({{ Ft.uw = Mem.ud;}});
+                    0x0: lwxc1({{ Fd.uw = Mem.uw;}});
+                    0x1: ldxc1({{ Fd.ud = Mem.ud;}});
+                    0x5: luxc1({{ Fd.uw = Mem.ud;}},
+                               {{ EA = (Rs + Rt) & ~7; }});
                 }
             }
 
             0x1: decode FUNCTION_LO {
                 format StoreIndexedMemory {
-                    0x0: swxc1({{ Mem.uw = Ft.uw;}});
-                    0x1: sdxc1({{ Mem.ud = Ft.ud;}});
-                    0x5: suxc1({{ Mem.ud = Ft.ud;}});
+                    0x0: swxc1({{ Mem.uw = Fs.uw;}});
+                    0x1: sdxc1({{ Mem.ud = Fs.ud;}});
+                    0x5: suxc1({{ Mem.ud = Fs.ud;}},
+                               {{ EA = (Rs + Rt) & ~7; }});
                 }
 
                 0x7: Prefetch::prefx({{ EA = Rs + Rt; }});
@@ -991,7 +997,7 @@ decode OPCODE_HI default Unknown::unknown() {
         0x7: decode FUNCTION_HI {
             0x0: decode FUNCTION_LO {
                 format BasicOp {
-                    0x1: ext({{ Rt.uw = bits(Rs.uw, MSB+LSB, LSB); }});
+                    0x0: ext({{ Rt.uw = bits(Rs.uw, MSB+LSB, LSB); }});
                     0x4: ins({{ Rt.uw = bits(Rt.uw, 31, MSB+1) << (MSB+1) |
                                         bits(Rs.uw, MSB-LSB, 0) << LSB |
                                         bits(Rt.uw, LSB-1, 0);
@@ -1014,8 +1020,8 @@ decode OPCODE_HI default Unknown::unknown() {
                                           Rt.uw<7:0>   << 8  |
                                           Rt.uw<15:8>;
                     }});
-                    0x10: seb({{ Rd.sw = Rt.sw<7:0>}});
-                    0x18: seh({{ Rd.sw = Rt.sw<15:0>}});
+                    0x10: seb({{ Rd.sw = Rt.sb; }});
+                    0x18: seh({{ Rd.sw = Rt.sh; }});
                 }
             }
 
diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa
index f52247056..cf6d3de74 100644
--- a/src/arch/mips/isa/formats/mem.isa
+++ b/src/arch/mips/isa/formats/mem.isa
@@ -58,14 +58,8 @@ output header {{
                StaticInstPtr _memAccPtr = nullStaticInstPtr)
             : MipsStaticInst(mnem, _machInst, __opClass),
               memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr),
-              disp(OFFSET)
+              disp(sext<16>(OFFSET))
         {
-            //If Bit 15 is 1 then Sign Extend
-            int32_t temp = disp & 0x00008000;
-
-            if (temp > 0) {
-                disp |= 0xFFFF0000;
-            }
         }
 
         std::string
@@ -77,6 +71,24 @@ output header {{
         const StaticInstPtr &memAccInst() const { return memAccPtr; }
     };
 
+     /**
+     * Base class for a few miscellaneous memory-format insts
+     * that don't interpret the disp field
+     */
+    class MemoryNoDisp : public Memory
+    {
+      protected:
+        /// Constructor
+        MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
+                     StaticInstPtr _eaCompPtr = nullStaticInstPtr,
+                     StaticInstPtr _memAccPtr = nullStaticInstPtr)
+            : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr)
+        {
+        }
+
+        std::string
+        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    };
 }};
 
 
@@ -84,10 +96,18 @@ output decoder {{
     std::string
     Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
     {
-        return csprintf("%-10s %c%d,%d(r%d)", mnemonic,
+        return csprintf("%-10s %c%d, %d(r%d)", mnemonic,
                         flags[IsFloating] ? 'f' : 'r', RT, disp, RS);
     }
 
+    std::string
+    MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+    {
+        return csprintf("%-10s %c%d, r%d(r%d)", mnemonic,
+                        flags[IsFloating] ? 'f' : 'r',
+                        flags[IsFloating] ? FD : RD,
+                        RS, RT);
+    }
 }};
 
 def template LoadStoreDeclare {{
diff --git a/src/arch/mips/regfile/float_regfile.hh b/src/arch/mips/regfile/float_regfile.hh
index d1a60298a..e260f681c 100644
--- a/src/arch/mips/regfile/float_regfile.hh
+++ b/src/arch/mips/regfile/float_regfile.hh
@@ -24,8 +24,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Korey Sewell
  */
 
 #ifndef __ARCH_MIPS_FLOAT_REGFILE_HH__
@@ -34,13 +32,14 @@
 #include "arch/mips/types.hh"
 #include "arch/mips/constants.hh"
 #include "base/misc.hh"
+#include "base/bitfield.hh"
 #include "config/full_system.hh"
 #include "sim/byteswap.hh"
 #include "sim/faults.hh"
 #include "sim/host.hh"
 
 class Checkpoint;
-class ThreadContext;
+class ExecContext;
 class Regfile;
 
 namespace MipsISA
@@ -103,6 +102,7 @@ namespace MipsISA
 
         Fault setReg(int floatReg, const FloatReg &val, int width)
         {
+            using namespace std;
             switch(width)
             {
               case SingleWidth:
@@ -117,8 +117,8 @@ namespace MipsISA
                 {
                     const void *double_ptr = &val;
                     FloatReg64 temp_double = *(FloatReg64 *) double_ptr;
-                    regs[floatReg + 1] = temp_double >> 32;
-                    regs[floatReg] = 0x0000FFFF & temp_double;
+                    regs[floatReg + 1] = bits(temp_double, 63, 32);
+                    regs[floatReg] = bits(temp_double, 31, 0);
                     break;
                 }
 
@@ -140,8 +140,8 @@ namespace MipsISA
                 break;
 
               case DoubleWidth:
-                regs[floatReg + 1] = val >> 32;
-                regs[floatReg] = val;
+                regs[floatReg + 1] = bits(val, 63, 32);
+                regs[floatReg] = bits(val, 31, 0);
                 break;
 
               default: