diff options
author | Gabe Black <gabeblack@google.com> | 2018-11-19 17:20:31 -0800 |
---|---|---|
committer | Gabe Black <gabeblack@google.com> | 2018-12-20 19:27:51 +0000 |
commit | 88bbabe93f339f9db301caf43bf2cca2a0e8048c (patch) | |
tree | 66323afaa9348f392deafe11d88973fd3034001b /src/arch | |
parent | 67d58e81825d7dff17def2cfeedf5d958141be55 (diff) | |
download | gem5-88bbabe93f339f9db301caf43bf2cca2a0e8048c.tar.xz |
arch, cpu: Remove float type accessors.
Use the binary accessors instead.
Change-Id: Iff1877e92c79df02b3d13635391a8c2f025776a2
Reviewed-on: https://gem5-review.googlesource.com/c/14457
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/arch')
-rw-r--r-- | src/arch/alpha/ev5.cc | 2 | ||||
-rw-r--r-- | src/arch/arm/tracers/tarmac_record.cc | 2 | ||||
-rw-r--r-- | src/arch/arm/utility.cc | 2 | ||||
-rw-r--r-- | src/arch/mips/utility.cc | 4 |
4 files changed, 5 insertions, 5 deletions
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc index ae8efa4e6..6a5d6afdc 100644 --- a/src/arch/alpha/ev5.cc +++ b/src/arch/alpha/ev5.cc @@ -88,7 +88,7 @@ zeroRegisters(CPU *cpu) // (no longer very clean due to the change in setIntReg() in the // cpu model. Consider changing later.) cpu->thread->setIntReg(ZeroReg, 0); - cpu->thread->setFloatReg(ZeroReg, 0.0); + cpu->thread->setFloatRegBits(ZeroReg, 0); } //////////////////////////////////////////////////////////////////////// diff --git a/src/arch/arm/tracers/tarmac_record.cc b/src/arch/arm/tracers/tarmac_record.cc index 7034d2586..5dbb847e5 100644 --- a/src/arch/arm/tracers/tarmac_record.cc +++ b/src/arch/arm/tracers/tarmac_record.cc @@ -235,7 +235,7 @@ TarmacTracerRecord::TraceRegEntry::updateFloat( regValid = true; regName = "f" + std::to_string(regRelIdx); - valueLo = thread->readFloatReg(regRelIdx); + valueLo = bitsToFloat32(thread->readFloatRegBits(regRelIdx)); } void diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc index d30d54a40..1dc7fc047 100644 --- a/src/arch/arm/utility.cc +++ b/src/arch/arm/utility.cc @@ -152,7 +152,7 @@ copyRegs(ThreadContext *src, ThreadContext *dest) dest->setIntRegFlat(i, src->readIntRegFlat(i)); for (int i = 0; i < NumFloatRegs; i++) - dest->setFloatRegFlat(i, src->readFloatRegFlat(i)); + dest->setFloatRegBitsFlat(i, src->readFloatRegBitsFlat(i)); for (int i = 0; i < NumVecRegs; i++) dest->setVecRegFlat(i, src->readVecRegFlat(i)); diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc index 2a9a8d83c..c8163b752 100644 --- a/src/arch/mips/utility.cc +++ b/src/arch/mips/utility.cc @@ -225,7 +225,7 @@ zeroRegisters(CPU *cpu) // (no longer very clean due to the change in setIntReg() in the // cpu model. Consider changing later.) cpu->thread->setIntReg(ZeroReg, 0); - cpu->thread->setFloatReg(ZeroReg, 0.0); + cpu->thread->setFloatRegBits(ZeroReg, 0); } void @@ -247,7 +247,7 @@ copyRegs(ThreadContext *src, ThreadContext *dest) // Then loop through the floating point registers. for (int i = 0; i < NumFloatRegs; i++) - dest->setFloatRegFlat(i, src->readFloatRegFlat(i)); + dest->setFloatRegBitsFlat(i, src->readFloatRegBitsFlat(i)); // Would need to add condition-code regs if implemented assert(NumCCRegs == 0); |