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authorGabe Black <gblack@eecs.umich.edu>2010-07-15 02:11:56 -0700
committerGabe Black <gblack@eecs.umich.edu>2010-07-15 02:11:56 -0700
commit8cec87056824782e061eac152b83432899d9b6d9 (patch)
tree58033e5bee79ae6c446efc763539ae769776ebbb /src/arch
parent4e3183cb1e5d4081fa7688bf89f8c776c52ec393 (diff)
downloadgem5-8cec87056824782e061eac152b83432899d9b6d9.tar.xz
ARM: Make an SRS instruction with a bad mode cause an undefined instruction fault.
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm/isa/formats/mem.isa2
-rw-r--r--src/arch/arm/isa/formats/uncond.isa2
2 files changed, 4 insertions, 0 deletions
diff --git a/src/arch/arm/isa/formats/mem.isa b/src/arch/arm/isa/formats/mem.isa
index 59a6f126a..f7830eff3 100644
--- a/src/arch/arm/isa/formats/mem.isa
+++ b/src/arch/arm/isa/formats/mem.isa
@@ -282,6 +282,8 @@ def format Thumb32SrsRfe() {{
}
} else {
const uint32_t mode = bits(machInst, 4, 0);
+ if (badMode((OperatingMode)mode))
+ return new Unknown(machInst);
if (!add && !wb) {
return new %(srs)s(machInst, mode,
SrsOp::DecrementBefore, wb);
diff --git a/src/arch/arm/isa/formats/uncond.isa b/src/arch/arm/isa/formats/uncond.isa
index f4cc16262..4fa707b2b 100644
--- a/src/arch/arm/isa/formats/uncond.isa
+++ b/src/arch/arm/isa/formats/uncond.isa
@@ -166,6 +166,8 @@ def format ArmUnconditional() {{
const uint32_t val = ((machInst >> 20) & 0x5);
if (val == 0x4) {
const uint32_t mode = bits(machInst, 4, 0);
+ if (badMode((OperatingMode)mode))
+ return new Unknown(machInst);
switch (bits(machInst, 24, 21)) {
case 0x2:
return new %(srs)s(machInst, mode,