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authorGabe Black <gblack@eecs.umich.edu>2009-04-19 04:56:22 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-04-19 04:56:22 -0700
commitb8f81c62a29b59d8de18476726cf2b7ac7cea1f5 (patch)
treedd6d2eaca9d397d20d77bcb6b454ef1e210655df /src/arch
parent750f5a0a67ccbce9b11c8ad308863be87ce89fbc (diff)
downloadgem5-b8f81c62a29b59d8de18476726cf2b7ac7cea1f5.tar.xz
X86: Implement a locking version of XCHG.
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py15
1 files changed, 15 insertions, 0 deletions
diff --git a/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py
index 3f243f5d8..521be95e5 100644
--- a/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py
+++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py
@@ -95,4 +95,19 @@ def macroop XCHG_P_R
st reg, seg, riprel, disp
mov reg, reg, t1
};
+
+def macroop XCHG_LOCKED_M_R
+{
+ ldstl t1, seg, sib, disp
+ stul reg, seg, sib, disp
+ mov reg, reg, t1
+};
+
+def macroop XCHG_LOCKED_P_R
+{
+ rdip t7
+ ldstl t1, seg, riprel, disp
+ stul reg, seg, riprel, disp
+ mov reg, reg, t1
+};
'''