mem: Remove threadId from memory request class

In general, the ThreadID parameter is unnecessary in the memory system
as the ContextID is what is used for the purposes of locks/wakeups.
Since we allocate sequential ContextIDs for each thread on MT-enabled
CPUs, ThreadID is unnecessary as the CPUs can identify the requesting
thread through sideband info (SenderState / LSQ entries) or ContextID
offset from the base ContextID for a cpu.

This is a re-spin of 20264eb after the revert (bd1c6789) and includes
some fixes of that commit.

4 files changed, 16 insertions, 17 deletions

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 6f66e5ae1..d3286a6b0 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1521,8 +1521,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
               // with unexpected atomic snoop requests.
               warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
               Request req(0, val, 1, flags,  Request::funcMasterId,
-                          tc->pcState().pc(), tc->contextId(),
-                          tc->threadId());
+                          tc->pcState().pc(), tc->contextId());
               fault = tc->getDTBPtr()->translateFunctional(&req, tc, mode, tranType);
               TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
               HCR   hcr   = readMiscRegNoEffect(MISCREG_HCR);
@@ -1768,7 +1767,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
                 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
                 req->setVirt(0, val, 1, flags,  Request::funcMasterId,
                                tc->pcState().pc());
-                req->setThreadContext(tc->contextId(), tc->threadId());
+                req->setContext(tc->contextId());
                 fault = tc->getDTBPtr()->translateFunctional(req, tc, mode,
                                                              tranType);
 
diff --git a/src/arch/arm/vtophys.cc b/src/arch/arm/vtophys.cc
index 3aad35818..24fc5a5c7 100644
--- a/src/arch/arm/vtophys.cc
+++ b/src/arch/arm/vtophys.cc
@@ -69,7 +69,7 @@ try_translate(ThreadContext *tc, Addr addr)
     Fault fault;
     // Set up a functional memory Request to pass to the TLB
     // to get it to translate the vaddr to a paddr
-    Request req(0, addr, 64, 0x40, -1, 0, 0, 0);
+    Request req(0, addr, 64, 0x40, -1, 0, 0);
     ArmISA::TLB *tlb;
 
     // Check the TLBs for a translation
diff --git a/src/arch/hsail/insts/mem.hh b/src/arch/hsail/insts/mem.hh
index 29091f9d1..f2792cd49 100644
--- a/src/arch/hsail/insts/mem.hh
+++ b/src/arch/hsail/insts/mem.hh
@@ -479,7 +479,7 @@ namespace HsailISA
                         } else {
                             Request *req = new Request(0, vaddr, sizeof(c0), 0,
                                           gpuDynInst->computeUnit()->masterId(),
-                                          0, gpuDynInst->wfDynId, i);
+                                          0, gpuDynInst->wfDynId);
 
                             gpuDynInst->setRequestFlags(req);
                             PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
@@ -528,7 +528,7 @@ namespace HsailISA
                     // create request
                     Request *req = new Request(0, 0, 0, 0,
                                   gpuDynInst->computeUnit()->masterId(),
-                                  0, gpuDynInst->wfDynId, -1);
+                                  0, gpuDynInst->wfDynId);
                     req->setFlags(Request::ACQUIRE);
                     gpuDynInst->computeUnit()->injectGlobalMemFence(gpuDynInst, false, req);
                 }
@@ -974,7 +974,7 @@ namespace HsailISA
                     // create request
                     Request *req = new Request(0, 0, 0, 0,
                                   gpuDynInst->computeUnit()->masterId(),
-                                  0, gpuDynInst->wfDynId, -1);
+                                  0, gpuDynInst->wfDynId);
                     req->setFlags(Request::RELEASE);
                     gpuDynInst->computeUnit()->injectGlobalMemFence(gpuDynInst, false, req);
 
@@ -1026,7 +1026,7 @@ namespace HsailISA
                             Request *req =
                               new Request(0, vaddr, sizeof(c0), 0,
                                           gpuDynInst->computeUnit()->masterId(),
-                                          0, gpuDynInst->wfDynId, i);
+                                          0, gpuDynInst->wfDynId);
 
                             gpuDynInst->setRequestFlags(req);
                             PacketPtr pkt = new Packet(req, MemCmd::WriteReq);
@@ -1366,7 +1366,7 @@ namespace HsailISA
                     // create request
                     Request *req = new Request(0, 0, 0, 0,
                                   gpuDynInst->computeUnit()->masterId(),
-                                  0, gpuDynInst->wfDynId, -1);
+                                  0, gpuDynInst->wfDynId);
                     req->setFlags(Request::RELEASE);
                     gpuDynInst->computeUnit()->injectGlobalMemFence(gpuDynInst, false, req);
 
@@ -1477,7 +1477,7 @@ namespace HsailISA
                         Request *req =
                             new Request(0, vaddr, sizeof(c0), 0,
                                         gpuDynInst->computeUnit()->masterId(),
-                                        0, gpuDynInst->wfDynId, i,
+                                        0, gpuDynInst->wfDynId,
                                         gpuDynInst->makeAtomicOpFunctor<c0>(e,
                                         f, this->opType));
 
@@ -1533,7 +1533,7 @@ namespace HsailISA
                     // create request
                     Request *req = new Request(0, 0, 0, 0,
                                   gpuDynInst->computeUnit()->masterId(),
-                                  0, gpuDynInst->wfDynId, -1);
+                                  0, gpuDynInst->wfDynId);
                     req->setFlags(Request::ACQUIRE);
                     gpuDynInst->computeUnit()->injectGlobalMemFence(gpuDynInst, false, req);
                 }
diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh
index a5ff467b3..a1d89de99 100644
--- a/src/arch/mips/locked_mem.hh
+++ b/src/arch/mips/locked_mem.hh
@@ -79,9 +79,9 @@ handleLockedRead(XC *xc, Request *req)
 {
     xc->setMiscReg(MISCREG_LLADDR, req->getPaddr() & ~0xf);
     xc->setMiscReg(MISCREG_LLFLAG, true);
-    DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link"
+    DPRINTF(LLSC, "[cid:%i]: Load-Link Flag Set & Load-Link"
                   " Address set to %x.\n",
-            req->threadId(), req->getPaddr() & ~0xf);
+            req->contextId(), req->getPaddr() & ~0xf);
 }
 
 template <class XC>
@@ -123,13 +123,13 @@ handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
             }
 
             if (!lock_flag){
-                DPRINTF(LLSC, "[tid:%i]: Lock Flag Set, "
+                DPRINTF(LLSC, "[cid:%i]: Lock Flag Set, "
                               "Store Conditional Failed.\n",
-                        req->threadId());
+                        req->contextId());
             } else if ((req->getPaddr() & ~0xf) != lock_addr) {
-                DPRINTF(LLSC, "[tid:%i]: Load-Link Address Mismatch, "
+                DPRINTF(LLSC, "[cid:%i]: Load-Link Address Mismatch, "
                               "Store Conditional Failed.\n",
-                        req->threadId());
+                        req->contextId());
             }
             // store conditional failed already, so don't issue it to mem
             return false;