diff options
| author | Andrew Bardsley <Andrew.Bardsley@arm.com> | 2014-09-12 10:22:47 -0400 |
|---|---|---|
| committer | Andrew Bardsley <Andrew.Bardsley@arm.com> | 2014-09-12 10:22:47 -0400 |
| commit | c8b919aba27a41adb7f75aeace358e4d31c47b76 (patch) | |
| tree | 49f918dad678e83f7d04e58f20f863519d412f6f /src/arch | |
| parent | 2b4906fc64984f9970186e6894f19f0f677a9fd4 (diff) | |
| download | gem5-c8b919aba27a41adb7f75aeace358e4d31c47b76.tar.xz | |
style: Fix line continuation, especially in debug messages
This patch closes a number of space gaps in debug messages caused by
the incorrect use of line continuation within strings. (There's also
one consistency change to a similar, but correct, use of line
continuation)
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/arm/faults.cc | 4 | ||||
| -rw-r--r-- | src/arch/arm/table_walker.cc | 4 | ||||
| -rw-r--r-- | src/arch/arm/tlb.cc | 10 |
3 files changed, 9 insertions, 9 deletions
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc index 6c1992dd6..94a82b9d5 100644 --- a/src/arch/arm/faults.cc +++ b/src/arch/arm/faults.cc @@ -1120,8 +1120,8 @@ DataAbort::ec(ThreadContext *tc) const if (to64) { // AArch64 if (source == ArmFault::AsynchronousExternalAbort) { - panic("Asynchronous External Abort should be handled with \ - SystemErrors (SErrors)!"); + panic("Asynchronous External Abort should be handled with " + "SystemErrors (SErrors)!"); } if (toEL == fromEL) return EC_DATA_ABORT_CURR_EL; diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc index 757dac695..5f9d9b20d 100644 --- a/src/arch/arm/table_walker.cc +++ b/src/arch/arm/table_walker.cc @@ -1116,8 +1116,8 @@ TableWalker::memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr, } } } - DPRINTF(TLBVerbose, "memAttrs: shareable: %d, innerAttrs: %d, \ - outerAttrs: %d\n", + DPRINTF(TLBVerbose, "memAttrs: shareable: %d, innerAttrs: %d, " + "outerAttrs: %d\n", te.shareable, te.innerAttrs, te.outerAttrs); te.setAttributes(false); } diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index 37cf9b149..ece4e5a1c 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -163,7 +163,7 @@ TLB::lookup(Addr va, uint16_t asn, uint8_t vmid, bool hyp, bool secure, retval ? retval->pAddr(va) : 0, retval ? retval->ap : 0, retval ? retval->ns : 0, retval ? retval->nstid : 0, retval ? retval->global : 0, retval ? retval->asid : 0, - retval ? retval->el : 0, retval ? retval->el : 0); + retval ? retval->el : 0); return retval; } @@ -1027,8 +1027,8 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, temp_te.outerShareable = false; } temp_te.setAttributes(long_desc_format); - DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable:\ - %d, innerAttrs: %d, outerAttrs: %d, isStage2: %d\n", + DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable: " + "%d, innerAttrs: %d, outerAttrs: %d, isStage2: %d\n", temp_te.shareable, temp_te.innerAttrs, temp_te.outerAttrs, isStage2); setAttr(temp_te.attributes); @@ -1052,8 +1052,8 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, if (te != NULL) { // Set memory attributes DPRINTF(TLBVerbose, - "Setting memory attributes: shareable: %d, innerAttrs: %d, \ - outerAttrs: %d, mtype: %d, isStage2: %d\n", + "Setting memory attributes: shareable: %d, innerAttrs: %d, " + "outerAttrs: %d, mtype: %d, isStage2: %d\n", te->shareable, te->innerAttrs, te->outerAttrs, static_cast<uint8_t>(te->mtype), isStage2); setAttr(te->attributes); |