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authorGabe Black <gblack@eecs.umich.edu>2009-04-19 03:17:14 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-04-19 03:17:14 -0700
commitd86cd1d2a02d2dd42e6b0f6e8bc8b8876c3d6152 (patch)
treeaaa3dfcc6a6284a2f2a0fc8e0d1b5a106c616d56 /src/arch
parentb4ad233c0c4aeb4f622a87ff6f7e5c4f072a2927 (diff)
downloadgem5-d86cd1d2a02d2dd42e6b0f6e8bc8b8876c3d6152.tar.xz
X86: Implement the load machine status word instruction (LMSW).
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/x86/isa/decoder/two_byte_opcodes.isa4
-rw-r--r--src/arch/x86/isa/insts/system/control_registers.py36
2 files changed, 38 insertions, 2 deletions
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index 0f6d59f3d..e55756fec 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -126,7 +126,7 @@
0x7: invlpga();
}
0x4: smsw_Rv();
- 0x6: lmsw_Rv();
+ 0x6: Inst::LMSW(Rv);
0x7: decode MODRM_RM {
0x0: Inst::SWAPGS();
0x1: rdtscp();
@@ -156,7 +156,7 @@
}
}
0x4: smsw_Mw();
- 0x6: lmsw_Mw();
+ 0x6: Inst::LMSW(Mw);
0x7: Inst::INVLPG(M);
default: Inst::UD2();
}
diff --git a/src/arch/x86/isa/insts/system/control_registers.py b/src/arch/x86/isa/insts/system/control_registers.py
index 902c01abb..c09cdf6e8 100644
--- a/src/arch/x86/isa/insts/system/control_registers.py
+++ b/src/arch/x86/isa/insts/system/control_registers.py
@@ -32,4 +32,40 @@ def macroop CLTS {
andi t1, t1, 0xF7, dataSize=1
wrcr 0, t1, dataSize=8
};
+
+def macroop LMSW_R {
+ rdcr t1, 0, dataSize=8
+ # This logic sets MP, EM, and TS to whatever is in the operand. It will
+ # set PE but not clear it.
+ limm t2, "~ULL(0xe)", dataSize=8
+ and t1, t1, t2, dataSize=8
+ andi t2, reg, 0xf, dataSize=8
+ or t1, t1, t2, dataSize=8
+ wrcr 0, t1, dataSize=8
+};
+
+def macroop LMSW_M {
+ ld t3, seg, sib, disp, dataSize=2
+ rdcr t1, 0, dataSize=8
+ # This logic sets MP, EM, and TS to whatever is in the operand. It will
+ # set PE but not clear it.
+ limm t2, "~ULL(0xe)", dataSize=8
+ and t1, t1, t2, dataSize=8
+ andi t2, t3, 0xf, dataSize=8
+ or t1, t1, t2, dataSize=8
+ wrcr 0, t1, dataSize=8
+};
+
+def macroop LMSW_P {
+ rdip t7, dataSize=asz
+ ld t3, seg, riprel, disp, dataSize=2
+ rdcr t1, 0, dataSize=8
+ # This logic sets MP, EM, and TS to whatever is in the operand. It will
+ # set PE but not clear it.
+ limm t2, "~ULL(0xe)", dataSize=8
+ and t1, t1, t2, dataSize=8
+ andi t2, t3, 0xf, dataSize=8
+ or t1, t1, t2, dataSize=8
+ wrcr 0, t1, dataSize=8
+};
'''