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authorMichael LeBeane <michael.lebeane@amd.com>2016-10-26 22:48:40 -0400
committerMichael LeBeane <michael.lebeane@amd.com>2016-10-26 22:48:40 -0400
commitdc16c1ceb806135dddb8c79ef4d5ecf1336f21bc (patch)
treefb8a0dde281883f6e817ad1854e6f8f0219a9fe4 /src/arch
parent48e43c9ad1cd292b494f3d05f9d13845dd1a6d1e (diff)
downloadgem5-dc16c1ceb806135dddb8c79ef4d5ecf1336f21bc.tar.xz
dev: Add m5 op to toggle synchronization for dist-gem5.
This patch adds the ability for an application to request dist-gem5 to begin/ end synchronization using an m5 op. When toggling on sync, all nodes agree on the next sync point based on the maximum of all nodes' ticks. CPUs are suspended until the sync point to avoid sending network messages until sync has been enabled. Toggling off sync acts like a global execution barrier, where all CPUs are disabled until every node reaches the toggle off point. This avoids tricky situations such as one node hitting a toggle off followed by a toggle on before the other nodes hit the first toggle off.
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/x86/isa/decoder/two_byte_opcodes.isa3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index 01e8e9b0c..772177d42 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -228,6 +228,9 @@
0x5b: m5_work_end({{
PseudoInst::workend(xc->tcBase(), Rdi, Rsi);
}}, IsNonSpeculative);
+ 0x62: m5togglesync({{
+ PseudoInst::togglesync(xc->tcBase());
+ }}, IsNonSpeculative, IsQuiesce);
default: Inst::UD2();
}
}