alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivate

activate(), suspend(), and halt() used on thread contexts had an optional
delay parameter. However this parameter was often ignored. Also, when used,
the delay was seemily arbitrarily set to 0 or 1 cycle (no other delays were
ever specified). This patch removes the delay parameter and 'Events'
associated with them across all ISAs and cores. Unused activate logic
is also removed.

7 files changed, 8 insertions, 8 deletions

diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh
index 1cd19cc95..72643cb16 100644
--- a/src/arch/alpha/utility.hh
+++ b/src/arch/alpha/utility.hh
@@ -68,7 +68,7 @@ void zeroRegisters(TC *tc);
 // Alpha IPR register accessors
 inline bool PcPAL(Addr addr) { return addr & 0x3; }
 inline void startupCPU(ThreadContext *tc, int cpuId)
-{ tc->activate(Cycles(0)); }
+{ tc->activate(); }
 
 ////////////////////////////////////////////////////////////////////////
 //
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 1eea743bb..2318f1aa9 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -104,7 +104,7 @@ void zeroRegisters(TC *tc);
 
 inline void startupCPU(ThreadContext *tc, int cpuId)
 {
-    tc->activate(Cycles(0));
+    tc->activate();
 }
 
 void copyRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/arch/mips/mt.hh b/src/arch/mips/mt.hh
index 64c765f19..b440eefa6 100755
--- a/src/arch/mips/mt.hh
+++ b/src/arch/mips/mt.hh
@@ -96,7 +96,7 @@ restoreThread(TC *tc)
 
         // TODO: SET PC WITH AN EVENT INSTEAD OF INSTANTANEOUSLY
         tc->pcState(restartPC);
-        tc->activate(Cycles(0));
+        tc->activate();
 
         warn("%i: Restoring thread %i in %s @ PC %x",
                 curTick(), tc->threadId(), tc->getCpuPtr()->name(), restartPC);
diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc
index ff410bad1..80047fbfd 100644
--- a/src/arch/mips/utility.cc
+++ b/src/arch/mips/utility.cc
@@ -231,7 +231,7 @@ zeroRegisters(CPU *cpu)
 void
 startupCPU(ThreadContext *tc, int cpuId)
 {
-    tc->activate(Cycles(0));
+    tc->activate();
 }
 
 void
diff --git a/src/arch/power/utility.hh b/src/arch/power/utility.hh
index 8d9f97436..907e451b9 100644
--- a/src/arch/power/utility.hh
+++ b/src/arch/power/utility.hh
@@ -59,7 +59,7 @@ void zeroRegisters(TC *tc);
 inline void
 startupCPU(ThreadContext *tc, int cpuId)
 {
-    tc->activate(Cycles(0));
+    tc->activate();
 }
 
 void
diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index 285a40c26..bc67f5ef8 100644
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -77,7 +77,7 @@ startupCPU(ThreadContext *tc, int cpuId)
 {
     // Other CPUs will get activated by IPIs
     if (cpuId == 0 || !FullSystem)
-        tc->activate(Cycles(0));
+        tc->activate();
 }
 
 void copyRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index fcd52d38a..d58498be2 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -203,12 +203,12 @@ void initCPU(ThreadContext *tc, int cpuId)
 void startupCPU(ThreadContext *tc, int cpuId)
 {
     if (cpuId == 0 || !FullSystem) {
-        tc->activate(Cycles(0));
+        tc->activate();
     } else {
         // This is an application processor (AP). It should be initialized to
         // look like only the BIOS POST has run on it and put then put it into
         // a halted state.
-        tc->suspend(Cycles(0));
+        tc->suspend();
     }
 }