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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:00 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:00 -0500 |
| commit | 003346077f466e4a5cabdd9e80ea05009bcf9204 (patch) | |
| tree | e38dedfd42a7698e33d6eab2991f75441521d437 /src/arch | |
| parent | 0d4c4cacabebdc01121b634fd82134f955f44a05 (diff) | |
| download | gem5-003346077f466e4a5cabdd9e80ea05009bcf9204.tar.xz | |
ARM: Flesh out 32 bit thumb load word decoding.
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/arm/isa/bitfields.isa | 3 | ||||
| -rw-r--r-- | src/arch/arm/isa/thumbdecode.isa | 17 | ||||
| -rw-r--r-- | src/arch/arm/types.hh | 3 |
3 files changed, 22 insertions, 1 deletions
diff --git a/src/arch/arm/isa/bitfields.isa b/src/arch/arm/isa/bitfields.isa index c9696a115..1dcbddec3 100644 --- a/src/arch/arm/isa/bitfields.isa +++ b/src/arch/arm/isa/bitfields.isa @@ -143,6 +143,7 @@ def bitfield HTOPCODE_8 htopcode8; def bitfield HTOPCODE_8_7 htopcode8_7; def bitfield HTOPCODE_8_6 htopcode8_6; def bitfield HTOPCODE_8_5 htopcode8_5; +def bitfield HTOPCODE_7 htopcode7; def bitfield HTOPCODE_6_5 htopcode6_5; def bitfield HTOPCODE_5_4 htopcode5_4; def bitfield HTOPCODE_4 htopcode4; @@ -151,6 +152,8 @@ def bitfield HTRN htrn; def bitfield HTS hts; def bitfield LTOPCODE_15 ltopcode15; +def bitfield LTOPCODE_11_8 ltopcode11_8; +def bitfield LTOPCODE_7_6 ltopcode7_6; def bitfield LTOPCODE_7_4 ltopcode7_4; def bitfield LTOPCODE_4 ltopcode4; diff --git a/src/arch/arm/isa/thumbdecode.isa b/src/arch/arm/isa/thumbdecode.isa index 682a98249..3d8e56a48 100644 --- a/src/arch/arm/isa/thumbdecode.isa +++ b/src/arch/arm/isa/thumbdecode.isa @@ -394,7 +394,22 @@ 0x1: decode HTOPCODE_6_5 { 0x0: WarnUnimpl::Load_byte_memory_hints(); 0x1: WarnUnimpl::Load_halfword_memory_hints(); - 0x2: WarnUnimpl::Load_word(); + 0x2: decode HTOPCODE_8 { + 0x0: decode HTRN { + 0xf: WarnUnimpl::ldr(); // literal A8-122 + default: decode HTOPCODE_7 { + 0x0: decode LTOPCODE_11_8 { + 0x0: decode LTOPCODE_7_6 { + 0x0: WarnUnimpl::ldr(); // register A8-122 + } + 0x9, 0xb, 0xc, 0xd, 0xf: + WarnUnimpl::ldr(); // immediate thumb A8-118 + 0xe: WarnUnimpl::ldrt(); // A8-176 + } + 0x1: WarnUnimpl::ldr(); // immediate thumb A8-118 + } + } + } 0x3: WarnUnimpl::undefined(); } } diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh index c3dcfe28a..23152d3cf 100644 --- a/src/arch/arm/types.hh +++ b/src/arch/arm/types.hh @@ -155,6 +155,7 @@ namespace ArmISA Bitfield<24, 23> htopcode8_7; Bitfield<24, 22> htopcode8_6; Bitfield<24, 21> htopcode8_5; + Bitfield<23> htopcode7; Bitfield<22, 21> htopcode6_5; Bitfield<21, 20> htopcode5_4; Bitfield<20> htopcode4; @@ -163,6 +164,8 @@ namespace ArmISA Bitfield<20> hts; Bitfield<15> ltopcode15; + Bitfield<11, 8> ltopcode11_8; + Bitfield<7, 6> ltopcode7_6; Bitfield<7, 4> ltopcode7_4; Bitfield<4> ltopcode4; |