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authorAli Saidi <Ali.Saidi@arm.com>2010-08-23 11:18:40 -0500
committerAli Saidi <Ali.Saidi@arm.com>2010-08-23 11:18:40 -0500
commit0c434b7f5650be8e742199e2d1efb5d642e210c5 (patch)
tree4747cd22b02f2edb3ac5de02b28f29c7e8251e26 /src/arch
parent5148c693d84062af857b5b8663e44434dba2b894 (diff)
downloadgem5-0c434b7f5650be8e742199e2d1efb5d642e210c5.tar.xz
ARM: Exclusive accesses must be double word aligned
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm/isa/insts/ldr.isa4
-rw-r--r--src/arch/arm/isa/insts/str.isa4
2 files changed, 6 insertions, 2 deletions
diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa
index cc6b6351b..6919bbca4 100644
--- a/src/arch/arm/isa/insts/ldr.isa
+++ b/src/arch/arm/isa/insts/ldr.isa
@@ -206,7 +206,9 @@ let {{
# Add memory request flags where necessary
if self.flavor == "exclusive":
self.memFlags.append("Request::LLSC")
- self.memFlags.append("ArmISA::TLB::AlignWord")
+ self.memFlags.append("ArmISA::TLB::AlignDoubleWord")
+ else:
+ self.memFlags.append("ArmISA::TLB::AlignWord")
# Disambiguate the class name for different flavors of loads
if self.flavor != "normal":
diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa
index 589758529..5b0e5b132 100644
--- a/src/arch/arm/isa/insts/str.isa
+++ b/src/arch/arm/isa/insts/str.isa
@@ -225,9 +225,11 @@ let {{
self.Name = self.nameFunc(self.post, self.add, self.writeback)
# Add memory request flags where necessary
- self.memFlags.append("ArmISA::TLB::AlignWord")
if self.flavor == "exclusive":
self.memFlags.append("Request::LLSC")
+ self.memFlags.append("ArmISA::TLB::AlignDoubleWord")
+ else:
+ self.memFlags.append("ArmISA::TLB::AlignWord")
# Disambiguate the class name for different flavors of stores
if self.flavor != "normal":