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authorGene Wu <Gene.Wu@arm.com>2010-08-23 11:18:41 -0500
committerGene Wu <Gene.Wu@arm.com>2010-08-23 11:18:41 -0500
commit23626d99af9469b5a86f510e0542846f5af65cbd (patch)
treecac4ec64670fe842af14a0183ae7d53b44ba9478 /src/arch
parent1fd104fc35ed5a1fa01e5709aba0dec58a5db6f5 (diff)
downloadgem5-23626d99af9469b5a86f510e0542846f5af65cbd.tar.xz
ARM: Make sure that software prefetch instructions can't change the state of the TLB
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm/faults.hh6
-rw-r--r--src/arch/arm/table_walker.cc5
-rw-r--r--src/arch/arm/tlb.cc5
3 files changed, 13 insertions, 3 deletions
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index d8684792c..f9d25abdf 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -87,6 +87,12 @@ class ArmFault : public FaultBase
MemoryAccessSynchronousParityError = 0x19,
TranslationTableWalkPrtyErr0 = 0x1c,
TranslationTableWalkPrtyErr1 = 0x1e,
+
+ // not a real fault. This is a status code
+ // to allow the translation function to inform
+ // the memory access function not to proceed
+ // for a Prefetch that misses in the TLB.
+ PrefetchTLBMiss
};
struct FaultVals
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 6dcb387a3..1d363c66f 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -439,11 +439,10 @@ TableWalker::doL1Descriptor()
* AccessFlag0
*/
- currState->fault =
- new DataAbort(currState->vaddr, NULL, currState->isWrite,
+ currState->fault = new DataAbort(currState->vaddr,
+ currState->l1Desc.domain(), currState->isWrite,
ArmFault::AccessFlag0);
}
-
if (currState->l1Desc.supersection()) {
panic("Haven't implemented supersections\n");
}
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index da2a34084..a70a20518 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -409,6 +409,11 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
TlbEntry *te = lookup(vaddr, context_id);
if (te == NULL) {
+ if (req->isPrefetch()){
+ //if the request is a prefetch don't attempt to fill the TLB
+ //or go any further with the memory access
+ return new PrefetchAbort(vaddr, ArmFault::PrefetchTLBMiss);
+ }
// start translation table walk, pass variables rather than
// re-retreaving in table walker for speed
DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n",