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| author | Ian Jiang <ianjiang.ict@gmail.com> | 2019-11-26 11:35:07 +0800 |
|---|---|---|
| committer | Ian Jiang <ianjiang.ict@gmail.com> | 2019-12-01 01:48:24 +0000 |
| commit | 258c04fc3fc7e69d9b6885776c0184515154675e (patch) | |
| tree | 98f0cb9a191f912de86ebe428831b80d61c08666 /src/arch | |
| parent | bcf041f257623e5c9e77d35b7531bae59edc0423 (diff) | |
| download | gem5-258c04fc3fc7e69d9b6885776c0184515154675e.tar.xz | |
arch-riscv: Fix disassembling of immediate for c.lui instruction
For compressed instruction c.lui, the 6-bit immediate is left-shifted by 12
bits in decoding. While the original Gem5 gives the left-shifted value
directly in disassembly.
This patch fixes the problem by adding a new template CILuiExecute to
resume the immediate before outputting it in disassembly.
Note: The immediate is sign-extended to 20-bit to be compatible with GCC.
Change-Id: If73f72d3e8f85a8b10ce7a323379d8ad6c4c3085
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22567
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/riscv/isa/formats/compressed.isa | 5 | ||||
| -rw-r--r-- | src/arch/riscv/isa/formats/standard.isa | 34 |
2 files changed, 38 insertions, 1 deletions
diff --git a/src/arch/riscv/isa/formats/compressed.isa b/src/arch/riscv/isa/formats/compressed.isa index 9c812e886..62d5b7567 100644 --- a/src/arch/riscv/isa/formats/compressed.isa +++ b/src/arch/riscv/isa/formats/compressed.isa @@ -54,7 +54,10 @@ def format CIOp(imm_code, code, imm_type='int64_t', *opt_flags) {{ header_output = ImmDeclare.subst(iop) decoder_output = ImmConstructor.subst(iop) decode_block = BasicDecode.subst(iop) - exec_output = ImmExecute.subst(iop) + if (name == "c_lui"): + exec_output = CILuiExecute.subst(iop) + else: + exec_output = ImmExecute.subst(iop) }}; def format CJOp(code, *opt_flags) {{ diff --git a/src/arch/riscv/isa/formats/standard.isa b/src/arch/riscv/isa/formats/standard.isa index a689c5750..2ffa2de88 100644 --- a/src/arch/riscv/isa/formats/standard.isa +++ b/src/arch/riscv/isa/formats/standard.isa @@ -90,6 +90,40 @@ def template ImmExecute {{ } }}; +def template CILuiExecute {{ + Fault + %(class_name)s::execute( + ExecContext *xc, Trace::InstRecord *traceData) const + { + Fault fault = NoFault; + + %(op_decl)s; + %(op_rd)s; + if (fault == NoFault) { + %(code)s; + if (fault == NoFault) { + %(op_wb)s; + } + } + return fault; + } + + std::string + %(class_name)s::generateDisassembly(Addr pc, + const SymbolTable *symtab) const + { + std::vector<RegId> indices = {%(regs)s}; + std::stringstream ss; + ss << mnemonic << ' '; + for (const RegId& idx: indices) + ss << registerName(idx) << ", "; + // To be compliant with GCC, the immediate is formated to a 20-bit + // signed integer. + ss << ((((uint64_t)imm) >> 12) & 0xFFFFF); + return ss.str(); + } +}}; + def template FenceExecute {{ Fault %(class_name)s::execute( |