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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-01-30 12:00:21 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-02-18 12:24:03 +0000 |
| commit | 291cc0665e3d62f8b7a284b0e54d0684ff6f2621 (patch) | |
| tree | 762a3f6c4bcfd17beefbb7d18e701305c9a91d2d /src/arch | |
| parent | 6a64cc100614f8325007e39a5defe88a2c3ba0b4 (diff) | |
| download | gem5-291cc0665e3d62f8b7a284b0e54d0684ff6f2621.tar.xz | |
arch-arm: Move GICv3 detection at startup time
At the moment the haveGicV3 parameter is used only to signal its
presence when reading the MISCREG_ID_AA64PFR0_EL1 register. It depends
on the system->getGIC pointing to a GICv3 model. However this pointer
is set in the System only at init time (after construction), which means
that the haveGICv3CPUInterface will always be false.
This patch is fixing this by moving the parameter initialization at
startup time, together with the cpu interface registration.
Change-Id: I8da6711ea741ecd0f78ec8ca60a8c3ae3bca2421
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16483
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/arm/isa.cc | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 97de97e6e..3b10f68a4 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -64,6 +64,7 @@ ISA::ISA(Params *p) _decoderFlavour(p->decoderFlavour), _vecRegRenameMode(Enums::Full), pmu(p->pmu), + haveGICv3CPUInterface(false), impdefAsNop(p->impdef_nop) { miscRegs[MISCREG_SCTLR_RST] = 0; @@ -96,13 +97,6 @@ ISA::ISA(Params *p) physAddrRange = 32; // dummy value } - // GICv3 CPU interface system registers are supported - haveGICv3CPUInterface = false; - - if (system && dynamic_cast<Gicv3 *>(system->getGIC())) { - haveGICv3CPUInterface = true; - } - // Initial rename mode depends on highestEL const_cast<Enums::VecRegRenameMode&>(_vecRegRenameMode) = highestELIs64 ? Enums::Full : Enums::Elem; @@ -388,6 +382,7 @@ ISA::startup(ThreadContext *tc) if (system) { Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC()); if (gicv3) { + haveGICv3CPUInterface = true; gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId())); gicv3CpuInterface->setISA(this); } |