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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-08-30 13:18:30 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-09-06 20:00:34 +0000 |
| commit | 2d2f51f9897059cea36329aea20a585e0308ccad (patch) | |
| tree | 7cbfc69414ad7f9677e0acb655e6af66bbe3dc14 /src/arch | |
| parent | d1251cd2c64a6bdbca38b65a7a9dc533c54f7f5c (diff) | |
| download | gem5-2d2f51f9897059cea36329aea20a585e0308ccad.tar.xz | |
arch-arm: Use same template across all MSR inst
Change-Id: Ifb9f1db288e401761b71ccf426e370c475e5663f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20622
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/arm/isa/insts/data64.isa | 33 |
1 files changed, 15 insertions, 18 deletions
diff --git a/src/arch/arm/isa/insts/data64.isa b/src/arch/arm/isa/insts/data64.isa index bb0334372..a2ffb9f5a 100644 --- a/src/arch/arm/isa/insts/data64.isa +++ b/src/arch/arm/isa/insts/data64.isa @@ -330,15 +330,26 @@ let {{ if (fault != NoFault) return fault; ''' - mrsCode = ''' + msr_check_code = ''' + MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()-> + flattenRegId(RegId(MiscRegClass, dest)).index(); + CPSR cpsr = Cpsr; + ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el; + %s + ''' % (msrMrs64EnabledCheckCode % ('Write'),) + + mrs_check_code = ''' MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()-> flattenRegId(RegId(MiscRegClass, op1)).index(); CPSR cpsr = Cpsr; ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el; %s - XDest = MiscOp1_ud; ''' % (msrMrs64EnabledCheckCode % ('Read'),) + + mrsCode = mrs_check_code + ''' + XDest = MiscOp1_ud; + ''' mrsIop = InstObjParams("mrs", "Mrs64", "RegMiscRegImmOp64", mrsCode, ["IsSerializeBefore"]) @@ -354,15 +365,9 @@ let {{ XDest = cpsr; ''') - msrCode = ''' - MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()-> - flattenRegId(RegId(MiscRegClass, dest)).index(); - CPSR cpsr = Cpsr; - ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el; - %s + msrCode = msr_check_code + ''' MiscDest_ud = XOp1; - ''' % (msrMrs64EnabledCheckCode % ('Write'),) - + ''' msrIop = InstObjParams("msr", "Msr64", "MiscRegRegImmOp64", msrCode, ["IsSerializeAfter", "IsNonSpeculative"]) @@ -378,14 +383,6 @@ let {{ CondCodesV = cpsr.v; ''') - msr_check_code = ''' - MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()-> - flattenRegId(RegId(MiscRegClass, dest)).index(); - CPSR cpsr = Cpsr; - ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el; - %s - ''' % (msrMrs64EnabledCheckCode % ('Write'),) - msrdczva_ea_code = msr_check_code msrdczva_ea_code += ''' |