sim,arch: Collapse the ISA specific versions of m5Syscall.

The x86 version doesn't do anything x86 specific, and so can be used
generically in sim/pseudo_inst.(hh|cc)

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I46c2a7d326bd7a95daa8611888051c180e92e446
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23177
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

10 files changed, 36 insertions, 67 deletions

diff --git a/src/arch/alpha/pseudo_inst.hh b/src/arch/alpha/pseudo_inst.hh
index 9f8b508c2..f15d0f572 100644
--- a/src/arch/alpha/pseudo_inst.hh
+++ b/src/arch/alpha/pseudo_inst.hh
@@ -32,14 +32,13 @@
 #define __ARCH_ALPHA_PSEUDO_INST_HH__
 
 #include "arch/generic/pseudo_inst.hh"
-#include "base/logging.hh"
 
-class ThreadContext;
+namespace AlphaISA
+{
 
-namespace AlphaISA {
-    using GenericISA::m5Syscall;
-    using GenericISA::m5PageFault;
-}
+using GenericISA::m5PageFault;
+
+} // namespace AlphaISA
 
 #endif // __ARCH_ALPHA_PSEUDO_INST_HH__
 
diff --git a/src/arch/arm/pseudo_inst.hh b/src/arch/arm/pseudo_inst.hh
index 50c725dcf..e687ed93d 100644
--- a/src/arch/arm/pseudo_inst.hh
+++ b/src/arch/arm/pseudo_inst.hh
@@ -32,14 +32,13 @@
 #define __ARCH_ARM_PSEUDO_INST_HH__
 
 #include "arch/generic/pseudo_inst.hh"
-#include "base/logging.hh"
 
-class ThreadContext;
+namespace ArmISA
+{
 
-namespace ArmISA {
-    using GenericISA::m5Syscall;
-    using GenericISA::m5PageFault;
-}
+using GenericISA::m5PageFault;
+
+} // namespace ArmISA
 
 #endif // __ARCH_ARM_PSEUDO_INST_HH__
 
diff --git a/src/arch/generic/pseudo_inst.cc b/src/arch/generic/pseudo_inst.cc
index 1c83d344f..ec4cbfd52 100644
--- a/src/arch/generic/pseudo_inst.cc
+++ b/src/arch/generic/pseudo_inst.cc
@@ -37,12 +37,6 @@ class ThreadContext;
 using namespace GenericISA;
 
 void
-GenericISA::m5Syscall(ThreadContext *tc)
-{
-    panic("m5Syscall not implemented for current ISA");
-}
-
-void
 GenericISA::m5PageFault(ThreadContext *tc)
 {
     panic("m5PageFault not implemented for current ISA");
diff --git a/src/arch/generic/pseudo_inst.hh b/src/arch/generic/pseudo_inst.hh
index 001334726..58b70fe9b 100644
--- a/src/arch/generic/pseudo_inst.hh
+++ b/src/arch/generic/pseudo_inst.hh
@@ -36,13 +36,6 @@ class ThreadContext;
 namespace GenericISA {
 
 /*
- * This function is executed when the simulation is executing the syscall
- * handler in System Emulation mode.
- */
-void
-m5Syscall(ThreadContext *tc);
-
-/*
  * This function is executed when the simulation is executing the pagefault
  * handler in System Emulation mode.
  */
diff --git a/src/arch/mips/pseudo_inst.hh b/src/arch/mips/pseudo_inst.hh
index 3741ebc71..1f65b344e 100644
--- a/src/arch/mips/pseudo_inst.hh
+++ b/src/arch/mips/pseudo_inst.hh
@@ -32,14 +32,13 @@
 #define __ARCH_MIPS_PSEUDO_INST_HH__
 
 #include "arch/generic/pseudo_inst.hh"
-#include "base/logging.hh"
 
-class ThreadContext;
+namespace MipsISA
+{
 
-namespace MipsISA {
-    using GenericISA::m5Syscall;
-    using GenericISA::m5PageFault;
-}
+using GenericISA::m5PageFault;
+
+} // namespace MipsISA
 
 #endif // __ARCH_MIPS_PSEUDO_INST_HH__
 
diff --git a/src/arch/power/pseudo_inst.hh b/src/arch/power/pseudo_inst.hh
index e1ecda238..99cd90528 100644
--- a/src/arch/power/pseudo_inst.hh
+++ b/src/arch/power/pseudo_inst.hh
@@ -32,14 +32,13 @@
 #define __ARCH_POWER_PSEUDO_INST_HH__
 
 #include "arch/generic/pseudo_inst.hh"
-#include "base/logging.hh"
 
-class ThreadContext;
+namespace PowerISA
+{
 
-namespace PowerISA {
-    using GenericISA::m5Syscall;
-    using GenericISA::m5PageFault;
-}
+using GenericISA::m5PageFault;
+
+} // namespace PowerISA
 
 #endif // __ARCH_POWER_PSEUDO_INST_HH__
 
diff --git a/src/arch/riscv/pseudo_inst.hh b/src/arch/riscv/pseudo_inst.hh
index 49cceb86b..642ffd610 100644
--- a/src/arch/riscv/pseudo_inst.hh
+++ b/src/arch/riscv/pseudo_inst.hh
@@ -32,14 +32,12 @@
 #define __ARCH_RISCV_PSEUDO_INST_HH__
 
 #include "arch/generic/pseudo_inst.hh"
-#include "base/logging.hh"
 
-class ThreadContext;
+namespace RiscvISA
+{
 
-namespace RiscvISA {
-    using GenericISA::m5Syscall;
-    using GenericISA::m5PageFault;
-}
+using GenericISA::m5PageFault;
 
-#endif // __ARCH_RISCV_PSEUDO_INST_HH__
+} // namespace RiscvISA
 
+#endif // __ARCH_RISCV_PSEUDO_INST_HH__
diff --git a/src/arch/sparc/pseudo_inst.hh b/src/arch/sparc/pseudo_inst.hh
index 5f9e576cc..34b9758b0 100644
--- a/src/arch/sparc/pseudo_inst.hh
+++ b/src/arch/sparc/pseudo_inst.hh
@@ -32,14 +32,13 @@
 #define __ARCH_SPARC_PSEUDO_INST_HH__
 
 #include "arch/generic/pseudo_inst.hh"
-#include "base/logging.hh"
 
-class ThreadContext;
+namespace SparcISA
+{
 
-namespace SparcISA {
-    using GenericISA::m5Syscall;
-    using GenericISA::m5PageFault;
-}
+using GenericISA::m5PageFault;
+
+} // namespace SparcISA
 
 #endif // __ARCH_SPARC_PSEUDO_INST_HH__
 
diff --git a/src/arch/x86/pseudo_inst.cc b/src/arch/x86/pseudo_inst.cc
index 68bc74acc..95d8ab8f8 100644
--- a/src/arch/x86/pseudo_inst.cc
+++ b/src/arch/x86/pseudo_inst.cc
@@ -41,19 +41,6 @@ using namespace X86ISA;
 namespace X86ISA {
 
 /*
- * This function is executed when the simulation is executing the syscall
- * handler in System Emulation mode.
- */
-void
-m5Syscall(ThreadContext *tc)
-{
-    DPRINTF(PseudoInst, "PseudoInst::m5Syscall()\n");
-
-    Fault fault;
-    tc->syscall(&fault);
-}
-
-/*
  * This function is executed when the simulation is executing the pagefault
  * handler in System Emulation mode.
  */
diff --git a/src/arch/x86/pseudo_inst.hh b/src/arch/x86/pseudo_inst.hh
index 5074d1fc3..d2a3cff7c 100644
--- a/src/arch/x86/pseudo_inst.hh
+++ b/src/arch/x86/pseudo_inst.hh
@@ -33,9 +33,11 @@
 
 class ThreadContext;
 
-namespace X86ISA {
-    void m5Syscall(ThreadContext *tc);
-    void m5PageFault(ThreadContext *tc);
-}
+namespace X86ISA
+{
+
+void m5PageFault(ThreadContext *tc);
+
+} // namespace X86ISA
 
 #endif // __ARCH_X86_PSEUDO_INST_HH__