arch-power: Simplify doubleword operand types

Currently, 'sq' and 'uq' are used to represent signed and
unsigned doublewords respectively. Since all recent Power
ISA specifications list 128-bit quadwords as a valid data
type, it may be misleading to use the current terminology
in case support for such operands are added in the future.
So, to simplify this, 'sd' and 'ud' are used to represent
signed and unsigned doublewords respectively.

Change-Id: Ie7831c596fc8f9ddfdf3b652c37cfe26484ebe01
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16602
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

2 files changed, 21 insertions, 16 deletions

diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 6bc19adb9..d2365bd5b 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -88,11 +88,16 @@ decode OPCODE default Unknown::unknown() {
         // Arithmetic instructions all use source registers Ra and Rb,
         // with destination register Rt.
         format IntArithOp {
-            75: mulhw({{ int64_t prod = Ra_sq * Rb_sq; Rt = prod >> 32; }});
-            11: mulhwu({{ uint64_t prod = Ra_uq * Rb_uq; Rt = prod >> 32; }});
-            235: mullw({{ int64_t prod = Ra_sq * Rb_sq; Rt = prod; }});
-            747: mullwo({{ int64_t src1 = Ra_sq; int64_t src2 = Rb; int64_t prod = src1 * src2; Rt = prod; }},
-                        true);
+            75: mulhw({{ int64_t prod = Ra_sd * Rb_sd; Rt = prod >> 32; }});
+            11: mulhwu({{ uint64_t prod = Ra_ud * Rb_ud; Rt = prod >> 32; }});
+            235: mullw({{ int64_t prod = Ra_sd * Rb_sd; Rt = prod; }});
+            747: mullwo({{
+                int64_t src1 = Ra_sd;
+                int64_t src2 = Rb;
+                int64_t prod = src1 * src2;
+                Rt = prod;
+            }},
+            true);
 
             491: divw({{
                 int32_t src1 = Ra_sw;
@@ -559,29 +564,29 @@ decode OPCODE default Unknown::unknown() {
             format FloatRCCheckOp {
                 72: fmr({{ Ft = Fb; }});
                 264: fabs({{
-                    Ft_uq = Fb_uq;
-                    Ft_uq = insertBits(Ft_uq, 63, 0); }});
+                    Ft_ud = Fb_ud;
+                    Ft_ud = insertBits(Ft_ud, 63, 0); }});
                 136: fnabs({{
-                    Ft_uq = Fb_uq;
-                    Ft_uq = insertBits(Ft_uq, 63, 1); }});
+                    Ft_ud = Fb_ud;
+                    Ft_ud = insertBits(Ft_ud, 63, 1); }});
                 40: fneg({{ Ft = -Fb; }});
                 8: fcpsgn({{
-                    Ft_uq = Fb_uq;
-                    Ft_uq = insertBits(Ft_uq, 63, Fa_uq<63:63>);
+                    Ft_ud = Fb_ud;
+                    Ft_ud = insertBits(Ft_ud, 63, Fa_ud<63:63>);
                 }});
-                583: mffs({{ Ft_uq = FPSCR; }});
+                583: mffs({{ Ft_ud = FPSCR; }});
                 134: mtfsfi({{
                     FPSCR = insertCRField(FPSCR, BF + (8 * (1 - W_FIELD)),
                                           U_FIELD);
                 }});
                 711: mtfsf({{
-                    if (L_FIELD == 1) { FPSCR = Fb_uq; }
+                    if (L_FIELD == 1) { FPSCR = Fb_ud; }
                     else {
                         for (int i = 0; i < 8; ++i) {
                             if (bits(FLM, i) == 1) {
                                 int k = 4 * (i + (8 * (1 - W_FIELD)));
                                 FPSCR = insertBits(FPSCR, k + 3, k,
-                                                   bits(Fb_uq, k + 3, k));
+                                                   bits(Fb_ud, k + 3, k));
                             }
                         }
                     }
diff --git a/src/arch/power/isa/operands.isa b/src/arch/power/isa/operands.isa
index fa481825f..98b91dc8a 100644
--- a/src/arch/power/isa/operands.isa
+++ b/src/arch/power/isa/operands.isa
@@ -35,8 +35,8 @@ def operand_types {{
     'uh' : 'uint16_t',
     'sw' : 'int32_t',
     'uw' : 'uint32_t',
-    'sq' : 'int64_t',
-    'uq' : 'uint64_t',
+    'sd' : 'int64_t',
+    'ud' : 'uint64_t',
     'sf' : 'float',
     'df' : 'double'
 }};