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| author | Andrea Mondelli <Andrea.Mondelli@ucf.edu> | 2019-03-19 13:56:59 -0400 |
|---|---|---|
| committer | Andrea Mondelli <Andrea.Mondelli@ucf.edu> | 2019-03-21 18:15:13 +0000 |
| commit | 487ea069be405844e1fcf4aa1ed274b74f601c39 (patch) | |
| tree | 6a96d3a17964ff7666d1bcd93a0bff6eaa0ab208 /src/arch | |
| parent | 699ba19096a5a8ea7eea93a2a8768910ca176b0b (diff) | |
| download | gem5-487ea069be405844e1fcf4aa1ed274b74f601c39.tar.xz | |
dev-arm: ambiguous use of getPort()
The recent introduction of getPort() creates a conflict with
the existing method used in arm MMU.
This patch rename the old getPort() in getDMAPort() according
to the returned value (DmaPort class type)
Change-Id: Ief3d83650fd6b08490522341631244be06e380ce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17469
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/arm/stage2_mmu.cc | 6 | ||||
| -rw-r--r-- | src/arch/arm/stage2_mmu.hh | 2 | ||||
| -rw-r--r-- | src/arch/arm/table_walker.cc | 2 | ||||
| -rw-r--r-- | src/arch/arm/tlb.cc | 2 |
4 files changed, 6 insertions, 6 deletions
diff --git a/src/arch/arm/stage2_mmu.cc b/src/arch/arm/stage2_mmu.cc index f043db29e..6235c223c 100644 --- a/src/arch/arm/stage2_mmu.cc +++ b/src/arch/arm/stage2_mmu.cc @@ -132,9 +132,9 @@ Stage2MMU::Stage2Translation::finish(const Fault &_fault, } if (_fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) { - parent.getPort().dmaAction(MemCmd::ReadReq, req->getPaddr(), numBytes, - event, data, tc->getCpuPtr()->clockPeriod(), - req->getFlags()); + parent.getDMAPort().dmaAction( + MemCmd::ReadReq, req->getPaddr(), numBytes, event, data, + tc->getCpuPtr()->clockPeriod(), req->getFlags()); } else { // We can't do the DMA access as there's been a problem, so tell the // event we're done diff --git a/src/arch/arm/stage2_mmu.hh b/src/arch/arm/stage2_mmu.hh index 8787089dc..69f2f52b8 100644 --- a/src/arch/arm/stage2_mmu.hh +++ b/src/arch/arm/stage2_mmu.hh @@ -110,7 +110,7 @@ class Stage2MMU : public SimObject * is used by the two table walkers, and is exposed externally and * connected through the stage-one table walker. */ - DmaPort& getPort() { return port; } + DmaPort& getDMAPort() { return port; } Fault readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr, uint8_t *data, int numBytes, Request::Flags flags, bool isFunctional); diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc index 21257de59..d310e9ee6 100644 --- a/src/arch/arm/table_walker.cc +++ b/src/arch/arm/table_walker.cc @@ -102,7 +102,7 @@ void TableWalker::setMMU(Stage2MMU *m, MasterID master_id) { stage2Mmu = m; - port = &m->getPort(); + port = &m->getDMAPort(); masterId = master_id; } diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index dc3c35bab..47c5f966f 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -1246,7 +1246,7 @@ TLB::translateComplete(const RequestPtr &req, ThreadContext *tc, Port * TLB::getTableWalkerPort() { - return &stage2Mmu->getPort(); + return &stage2Mmu->getDMAPort(); } void |