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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:01 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:01 -0500
commit4bbd73649d55fa59cf404cbd72bd68478d1115ff (patch)
treed0c309f1bd3b89b54326e458a1a7b3aea4046e83 /src/arch
parent462cf6f49b388558d1fe7aa7731500d0e9abcdef (diff)
downloadgem5-4bbd73649d55fa59cf404cbd72bd68478d1115ff.tar.xz
ARM: Decode 16 bit thumb register addressed memory instructions.
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm/isa/decoder/thumb.isa11
-rw-r--r--src/arch/arm/isa/formats/mem.isa40
2 files changed, 41 insertions, 10 deletions
diff --git a/src/arch/arm/isa/decoder/thumb.isa b/src/arch/arm/isa/decoder/thumb.isa
index 1518b04ea..aec9ebdfc 100644
--- a/src/arch/arm/isa/decoder/thumb.isa
+++ b/src/arch/arm/isa/decoder/thumb.isa
@@ -90,16 +90,7 @@
0xe, 0xf: WarnUnimpl::blx(); //register
}
0x2, 0x3: WarnUnimpl::ldr();
- default: decode TOPCODE_11_9 {
- 0x0: WarnUnimpl::str(); //register
- 0x1: WarnUnimpl::strh(); //register
- 0x2: WarnUnimpl::strb(); //register
- 0x3: WarnUnimpl::ldrsb(); //register
- 0x4: WarnUnimpl::ldr(); //register
- 0x5: WarnUnimpl::ldrh(); //register
- 0x6: WarnUnimpl::ldrb(); //register
- 0x7: WarnUnimpl::ldrsh(); //register
- }
+ default: Thumb16MemReg::thumb16MemReg();
}
0x3: decode TOPCODE_12_11 {
0x0: WarnUnimpl::str(); //immediate, thumb
diff --git a/src/arch/arm/isa/formats/mem.isa b/src/arch/arm/isa/formats/mem.isa
index bc3c1f720..1602997dd 100644
--- a/src/arch/arm/isa/formats/mem.isa
+++ b/src/arch/arm/isa/formats/mem.isa
@@ -358,6 +358,46 @@ def format Thumb32StoreSingle() {{
decode_block = decode % classNames
}};
+def format Thumb16MemReg() {{
+ decode = '''
+ {
+ const uint32_t opb = bits(machInst, 11, 9);
+ const uint32_t rt = bits(machInst, 2, 0);
+ const uint32_t rn = bits(machInst, 5, 3);
+ const uint32_t rm = bits(machInst, 8, 6);
+ switch (opb) {
+ case 0x0:
+ return new %(str)s(machInst, rt, rn, true, 0, LSL, rm);
+ case 0x1:
+ return new %(strh)s(machInst, rt, rn, true, 0, LSL, rm);
+ case 0x2:
+ return new %(strb)s(machInst, rt, rn, true, 0, LSL, rm);
+ case 0x3:
+ return new %(ldrsb)s(machInst, rt, rn, true, 0, LSL, rm);
+ case 0x4:
+ return new %(ldr)s(machInst, rt, rn, true, 0, LSL, rm);
+ case 0x5:
+ return new %(ldrh)s(machInst, rt, rn, true, 0, LSL, rm);
+ case 0x6:
+ return new %(ldrb)s(machInst, rt, rn, true, 0, LSL, rm);
+ case 0x7:
+ return new %(ldrsh)s(machInst, rt, rn, true, 0, LSL, rm);
+ }
+ }
+ '''
+ classNames = {
+ "str" : storeRegClassName(False, True, False),
+ "strh" : storeRegClassName(False, True, False, size=2),
+ "strb" : storeRegClassName(False, True, False, size=1),
+ "ldrsb" : loadRegClassName(False, True, False, sign=True, size=1),
+ "ldr" : loadRegClassName(False, True, False),
+ "ldrh" : loadRegClassName(False, True, False, size=2),
+ "ldrb" : loadRegClassName(False, True, False, size=1),
+ "ldrsh" : loadRegClassName(False, True, False, sign=True, size=2),
+ }
+ decode_block = decode % classNames
+}};
+
def format ArmLoadMemory(memacc_code, ea_code = {{ EA = Rn + disp; }},
mem_flags = [], inst_flags = []) {{
ea_code = ArmGenericCodeSubs(ea_code)