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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-02-13 15:14:34 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-04-29 08:49:25 +0000 |
| commit | 529284becb4610016bdea7a5a40d1be73e2ec697 (patch) | |
| tree | cf44884be90c9fde6409bed9aa50a492011889b9 /src/arch | |
| parent | 9305bb6e83d57fde96c78e7b11d50914935f57d5 (diff) | |
| download | gem5-529284becb4610016bdea7a5a40d1be73e2ec697.tar.xz | |
arch-arm: Report real instruction encoding when Undefined
When dumping the opcode that caused an Undefined Instruction, we just
want to dump the real instruction encoding, and not the extended version
with metabits (like thumb, bigThumb etc). This was not appening when
panicking in SE mode.
The patch is also replacing custom masking in the Unknown(64) disassembler
in favour of ArmStaticInstruction::encoding() helper.
Change-Id: I9eb6fd145d02b4b07bb51f0bd89ca014d6d5a6de
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18395
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/arm/faults.cc | 7 | ||||
| -rw-r--r-- | src/arch/arm/insts/misc.cc | 2 | ||||
| -rw-r--r-- | src/arch/arm/insts/misc64.cc | 2 |
3 files changed, 6 insertions, 5 deletions
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc index 665b2989c..9cd068f7f 100644 --- a/src/arch/arm/faults.cc +++ b/src/arch/arm/faults.cc @@ -749,15 +749,16 @@ UndefinedInstruction::invoke(ThreadContext *tc, const StaticInstPtr &inst) // If the mnemonic isn't defined this has to be an unknown instruction. assert(unknown || mnemonic != NULL); + auto arm_inst = static_cast<ArmStaticInst *>(inst.get()); if (disabled) { panic("Attempted to execute disabled instruction " - "'%s' (inst 0x%08x)", mnemonic, machInst); + "'%s' (inst 0x%08x)", mnemonic, arm_inst->encoding()); } else if (unknown) { panic("Attempted to execute unknown instruction (inst 0x%08x)", - machInst); + arm_inst->encoding()); } else { panic("Attempted to execute unimplemented instruction " - "'%s' (inst 0x%08x)", mnemonic, machInst); + "'%s' (inst 0x%08x)", mnemonic, arm_inst->encoding()); } } diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc index 3f2986525..8efb81a6c 100644 --- a/src/arch/arm/insts/misc.cc +++ b/src/arch/arm/insts/misc.cc @@ -324,7 +324,7 @@ RegImmRegShiftOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const std::string UnknownOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const { - return csprintf("%-10s (inst %#08x)", "unknown", machInst & mask(32)); + return csprintf("%-10s (inst %#08x)", "unknown", encoding()); } McrMrcMiscInst::McrMrcMiscInst(const char *_mnemonic, ExtMachInst _machInst, diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc index 7df2f76ed..c219bd9ad 100644 --- a/src/arch/arm/insts/misc64.cc +++ b/src/arch/arm/insts/misc64.cc @@ -78,7 +78,7 @@ RegRegRegImmOp64::generateDisassembly( std::string UnknownOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const { - return csprintf("%-10s (inst %#08x)", "unknown", machInst & mask(32)); + return csprintf("%-10s (inst %#08x)", "unknown", encoding()); } Fault |