x86: Replace htog and gtoh with htole and letoh.

We already know what endianness to use from within x86.

Change-Id: Ie92568efe8b23fbb7d9edad55fef09c6302cbe62
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22370
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

10 files changed, 50 insertions, 51 deletions

diff --git a/src/arch/x86/bios/e820.cc b/src/arch/x86/bios/e820.cc
index 6cb16c995..f4bb29866 100644
--- a/src/arch/x86/bios/e820.cc
+++ b/src/arch/x86/bios/e820.cc
@@ -49,7 +49,7 @@ using namespace X86ISA;
 template<class T>
 void writeVal(T val, PortProxy& proxy, Addr &addr)
 {
-    T guestVal = htog(val);
+    T guestVal = htole(val);
     proxy.writeBlob(addr, &guestVal, sizeof(T));
     addr += sizeof(T);
 }
@@ -62,7 +62,7 @@ void X86ISA::E820Table::writeTo(PortProxy& proxy, Addr countAddr, Addr addr)
     // would be capable of handling.
     assert(e820Nr <= 128);
 
-    uint8_t guestE820Nr = htog(e820Nr);
+    uint8_t guestE820Nr = htole(e820Nr);
 
     proxy.writeBlob(countAddr, &guestE820Nr, sizeof(guestE820Nr));
 
diff --git a/src/arch/x86/bios/intelmp.cc b/src/arch/x86/bios/intelmp.cc
index a9da25a8a..d87e4fc17 100644
--- a/src/arch/x86/bios/intelmp.cc
+++ b/src/arch/x86/bios/intelmp.cc
@@ -73,7 +73,7 @@ template<class T>
 uint8_t
 writeOutField(PortProxy& proxy, Addr addr, T val)
 {
-    uint64_t guestVal = X86ISA::htog(val);
+    uint64_t guestVal = htole(val);
     proxy.writeBlob(addr, &guestVal, sizeof(T));
 
     uint8_t checkSum = 0;
diff --git a/src/arch/x86/bios/smbios.cc b/src/arch/x86/bios/smbios.cc
index cd91d2d02..b1af8e9a1 100644
--- a/src/arch/x86/bios/smbios.cc
+++ b/src/arch/x86/bios/smbios.cc
@@ -82,7 +82,7 @@ X86ISA::SMBios::SMBiosStructure::writeOut(PortProxy& proxy, Addr addr)
     uint8_t length = getLength();
     proxy.writeBlob(addr + 1, &length, 1);
 
-    uint16_t handleGuest = X86ISA::htog(handle);
+    uint16_t handleGuest = htole(handle);
     proxy.writeBlob(addr + 2, &handleGuest, 2);
 
     return length + getStringLength();
@@ -179,17 +179,17 @@ X86ISA::SMBios::BiosInformation::writeOut(PortProxy& proxy, Addr addr)
     proxy.writeBlob(addr + 0x4, &vendor, 1);
     proxy.writeBlob(addr + 0x5, &version, 1);
 
-    uint16_t startingAddrSegmentGuest = X86ISA::htog(startingAddrSegment);
+    uint16_t startingAddrSegmentGuest = htole(startingAddrSegment);
     proxy.writeBlob(addr + 0x6, &startingAddrSegmentGuest, 2);
 
     proxy.writeBlob(addr + 0x8, &releaseDate, 1);
     proxy.writeBlob(addr + 0x9, &romSize, 1);
 
-    uint64_t characteristicsGuest = X86ISA::htog(characteristics);
+    uint64_t characteristicsGuest = htole(characteristics);
     proxy.writeBlob(addr + 0xA, &characteristicsGuest, 8);
 
     uint16_t characteristicExtBytesGuest =
-        X86ISA::htog(characteristicExtBytes);
+        htole(characteristicExtBytes);
     proxy.writeBlob(addr + 0x12, &characteristicExtBytesGuest, 2);
 
     proxy.writeBlob(addr + 0x14, &majorVer, 1);
@@ -257,14 +257,14 @@ X86ISA::SMBios::SMBiosTable::writeOut(PortProxy& proxy, Addr addr,
     // Then the length of the structure table which we'll find later
 
     uint32_t tableAddrGuest =
-        X86ISA::htog(smbiosHeader.intermediateHeader.tableAddr);
+        htole(smbiosHeader.intermediateHeader.tableAddr);
     proxy.writeBlob(addr + 0x18, &tableAddrGuest, 4);
     for (int i = 0; i < 4; i++) {
         intChecksum += tableAddrGuest;
         tableAddrGuest >>= 8;
     }
 
-    uint16_t numStructs = X86ISA::gtoh(structures.size());
+    uint16_t numStructs = letoh(structures.size());
     proxy.writeBlob(addr + 0x1C, &numStructs, 2);
     for (int i = 0; i < 2; i++) {
         intChecksum += numStructs;
@@ -296,7 +296,7 @@ X86ISA::SMBios::SMBiosTable::writeOut(PortProxy& proxy, Addr addr,
      * Header
      */
 
-    maxSize = X86ISA::htog(maxSize);
+    maxSize = htole(maxSize);
     proxy.writeBlob(addr + 0x8, &maxSize, 2);
     for (int i = 0; i < 2; i++) {
         mainChecksum += maxSize;
@@ -312,7 +312,7 @@ X86ISA::SMBios::SMBiosTable::writeOut(PortProxy& proxy, Addr addr,
      */
 
     uint16_t tableSize = offset;
-    tableSize = X86ISA::htog(tableSize);
+    tableSize = htole(tableSize);
     proxy.writeBlob(addr + 0x16, &tableSize, 2);
     for (int i = 0; i < 2; i++) {
         intChecksum += tableSize;
diff --git a/src/arch/x86/interrupts.cc b/src/arch/x86/interrupts.cc
index 80d2650ef..06bf41bd1 100644
--- a/src/arch/x86/interrupts.cc
+++ b/src/arch/x86/interrupts.cc
@@ -196,7 +196,7 @@ X86ISA::Interrupts::read(PacketPtr pkt)
     if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
         panic("Accessed more than one register at a time in the APIC!\n");
     ApicRegIndex reg = decodeAddr(offset);
-    uint32_t val = htog(readReg(reg));
+    uint32_t val = htole(readReg(reg));
     DPRINTF(LocalApic,
             "Reading Local APIC register %d at offset %#x as %#x.\n",
             reg, offset, val);
@@ -217,8 +217,8 @@ X86ISA::Interrupts::write(PacketPtr pkt)
     pkt->writeData(((uint8_t *)&val) + (offset & mask(3)));
     DPRINTF(LocalApic,
             "Writing Local APIC register %d at offset %#x as %#x.\n",
-            reg, offset, gtoh(val));
-    setReg(reg, gtoh(val));
+            reg, offset, letoh(val));
+    setReg(reg, letoh(val));
     pkt->makeAtomicResponse();
     return pioDelay;
 }
diff --git a/src/arch/x86/linux/system.cc b/src/arch/x86/linux/system.cc
index 04ab023b8..b4cd70e30 100644
--- a/src/arch/x86/linux/system.cc
+++ b/src/arch/x86/linux/system.cc
@@ -85,8 +85,7 @@ LinuxX86System::initState()
 
     // Generate a pointer of the right size and endianness to put into
     // commandLinePointer.
-    uint32_t guestCommandLineBuff =
-        X86ISA::htog((uint32_t)commandLineBuff);
+    uint32_t guestCommandLineBuff = htole((uint32_t)commandLineBuff);
     physProxy.writeBlob(commandLinePointer, &guestCommandLineBuff,
                         sizeof(guestCommandLineBuff));
 
diff --git a/src/arch/x86/memhelpers.hh b/src/arch/x86/memhelpers.hh
index 59db401c1..424b729b6 100644
--- a/src/arch/x86/memhelpers.hh
+++ b/src/arch/x86/memhelpers.hh
@@ -113,7 +113,7 @@ readMemAtomic(ExecContext *xc, Trace::InstRecord *traceData, Addr addr,
         // If LE to LE, this is a nop, if LE to BE, the actual data ends up
         // in the right place because the LSBs where at the low addresses on
         // access. This doesn't work for BE guests.
-        mem = gtoh(mem);
+        mem = letoh(mem);
         if (traceData)
             traceData->setData(mem);
     }
@@ -129,7 +129,7 @@ readPackedMemAtomic(ExecContext *xc, Addr addr, std::array<uint64_t, N> &mem,
     Fault fault = xc->readMem(addr, (uint8_t *)&real_mem,
                               sizeof(T) * N, flags);
     if (fault == NoFault) {
-        real_mem = gtoh(real_mem);
+        real_mem = letoh(real_mem);
         for (int i = 0; i < N; i++)
             mem[i] = real_mem[i];
     }
@@ -167,7 +167,7 @@ writePackedMem(ExecContext *xc, std::array<uint64_t, N> &mem, Addr addr,
     std::array<T, N> real_mem;
     for (int i = 0; i < N; i++)
         real_mem[i] = mem[i];
-    real_mem = htog(real_mem);
+    real_mem = htole(real_mem);
     return xc->writeMem((uint8_t *)&real_mem, sizeof(T) * N,
                         addr, flags, res);
 }
@@ -179,7 +179,7 @@ writeMemTiming(ExecContext *xc, Trace::InstRecord *traceData, uint64_t mem,
 {
     if (traceData)
         traceData->setData(mem);
-    mem = htog(mem);
+    mem = htole(mem);
     return xc->writeMem((uint8_t *)&mem, dataSize, addr, flags, res);
 }
 
@@ -209,11 +209,11 @@ writeMemAtomic(ExecContext *xc, Trace::InstRecord *traceData, uint64_t mem,
 {
     if (traceData)
         traceData->setData(mem);
-    uint64_t host_mem = htog(mem);
+    uint64_t host_mem = htole(mem);
     Fault fault =
           xc->writeMem((uint8_t *)&host_mem, dataSize, addr, flags, res);
     if (fault == NoFault && res)
-        *res = gtoh(*res);
+        *res = letoh(*res);
     return fault;
 }
 
@@ -239,7 +239,7 @@ writeMemAtomic(ExecContext *xc, Trace::InstRecord *traceData,
     }
 
     if (fault == NoFault && res)
-        *res = gtoh(*res);
+        *res = letoh(*res);
 
     return fault;
 }
diff --git a/src/arch/x86/mmapped_ipr.hh b/src/arch/x86/mmapped_ipr.hh
index 93c16d33d..27cb4de3b 100644
--- a/src/arch/x86/mmapped_ipr.hh
+++ b/src/arch/x86/mmapped_ipr.hh
@@ -63,7 +63,7 @@ namespace X86ISA
             Addr offset = pkt->getAddr() & mask(3);
             MiscRegIndex index = (MiscRegIndex)(
                 pkt->getAddr() / sizeof(RegVal));
-            RegVal data = htog(xc->readMiscReg(index));
+            RegVal data = htole(xc->readMiscReg(index));
             // Make sure we don't trot off the end of data.
             assert(offset + pkt->getSize() <= sizeof(RegVal));
             pkt->setData(((uint8_t *)&data) + offset);
@@ -80,11 +80,11 @@ namespace X86ISA
             Addr offset = pkt->getAddr() & mask(3);
             MiscRegIndex index = (MiscRegIndex)(
                 pkt->getAddr() / sizeof(RegVal));
-            RegVal data = htog(xc->readMiscRegNoEffect(index));
+            RegVal data = htole(xc->readMiscRegNoEffect(index));
             // Make sure we don't trot off the end of data.
             assert(offset + pkt->getSize() <= sizeof(RegVal));
             pkt->writeData(((uint8_t *)&data) + offset);
-            xc->setMiscReg(index, gtoh(data));
+            xc->setMiscReg(index, letoh(data));
             return Cycles(1);
         }
     }
diff --git a/src/arch/x86/nativetrace.cc b/src/arch/x86/nativetrace.cc
index 142a51cd7..3325e5849 100644
--- a/src/arch/x86/nativetrace.cc
+++ b/src/arch/x86/nativetrace.cc
@@ -44,28 +44,28 @@ void
 X86NativeTrace::ThreadState::update(NativeTrace *parent)
 {
     parent->read(this, sizeof(*this));
-    rax = X86ISA::gtoh(rax);
-    rcx = X86ISA::gtoh(rcx);
-    rdx = X86ISA::gtoh(rdx);
-    rbx = X86ISA::gtoh(rbx);
-    rsp = X86ISA::gtoh(rsp);
-    rbp = X86ISA::gtoh(rbp);
-    rsi = X86ISA::gtoh(rsi);
-    rdi = X86ISA::gtoh(rdi);
-    r8 = X86ISA::gtoh(r8);
-    r9 = X86ISA::gtoh(r9);
-    r10 = X86ISA::gtoh(r10);
-    r11 = X86ISA::gtoh(r11);
-    r12 = X86ISA::gtoh(r12);
-    r13 = X86ISA::gtoh(r13);
-    r14 = X86ISA::gtoh(r14);
-    r15 = X86ISA::gtoh(r15);
-    rip = X86ISA::gtoh(rip);
+    rax = letoh(rax);
+    rcx = letoh(rcx);
+    rdx = letoh(rdx);
+    rbx = letoh(rbx);
+    rsp = letoh(rsp);
+    rbp = letoh(rbp);
+    rsi = letoh(rsi);
+    rdi = letoh(rdi);
+    r8 = letoh(r8);
+    r9 = letoh(r9);
+    r10 = letoh(r10);
+    r11 = letoh(r11);
+    r12 = letoh(r12);
+    r13 = letoh(r13);
+    r14 = letoh(r14);
+    r15 = letoh(r15);
+    rip = letoh(rip);
     //This should be expanded if x87 registers are considered
     for (int i = 0; i < 8; i++)
-        mmx[i] = X86ISA::gtoh(mmx[i]);
+        mmx[i] = letoh(mmx[i]);
     for (int i = 0; i < 32; i++)
-        xmm[i] = X86ISA::gtoh(xmm[i]);
+        xmm[i] = letoh(xmm[i]);
 }
 
 void
diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc
index f90c764ee..09ff71f52 100644
--- a/src/arch/x86/process.cc
+++ b/src/arch/x86/process.cc
@@ -986,7 +986,7 @@ X86Process::argsInit(int pageSize,
 
     // figure out argc
     IntType argc = argv.size();
-    IntType guestArgc = X86ISA::htog(argc);
+    IntType guestArgc = htole(argc);
 
     // Write out the sentry void *
     IntType sentry_NULL = 0;
diff --git a/src/arch/x86/system.cc b/src/arch/x86/system.cc
index 2af9ff53c..704a37aba 100644
--- a/src/arch/x86/system.cc
+++ b/src/arch/x86/system.cc
@@ -224,23 +224,23 @@ X86System::initState()
     // Page Map Level 4
 
     // read/write, user, not present
-    uint64_t pml4e = X86ISA::htog(0x6);
+    uint64_t pml4e = htole<uint64_t>(0x6);
     for (int offset = 0; offset < (1 << PML4Bits) * 8; offset += 8) {
         physProxy.writeBlob(PageMapLevel4 + offset, (&pml4e), 8);
     }
     // Point to the only PDPT
-    pml4e = X86ISA::htog(0x7 | PageDirPtrTable);
+    pml4e = htole<uint64_t>(0x7 | PageDirPtrTable);
     physProxy.writeBlob(PageMapLevel4, (&pml4e), 8);
 
     // Page Directory Pointer Table
 
     // read/write, user, not present
-    uint64_t pdpe = X86ISA::htog(0x6);
+    uint64_t pdpe = htole<uint64_t>(0x6);
     for (int offset = 0; offset < (1 << PDPTBits) * 8; offset += 8)
         physProxy.writeBlob(PageDirPtrTable + offset, &pdpe, 8);
     // Point to the PDTs
     for (int table = 0; table < NumPDTs; table++) {
-        pdpe = X86ISA::htog(0x7 | PageDirTable[table]);
+        pdpe = htole<uint64_t>(0x7 | PageDirTable[table]);
         physProxy.writeBlob(PageDirPtrTable + table * 8, &pdpe, 8);
     }
 
@@ -251,7 +251,7 @@ X86System::initState()
     for (int table = 0; table < NumPDTs; table++) {
         for (int offset = 0; offset < (1 << PDTBits) * 8; offset += 8) {
             // read/write, user, present, 4MB
-            uint64_t pdte = X86ISA::htog(0x87 | base);
+            uint64_t pdte = htole(0x87 | base);
             physProxy.writeBlob(PageDirTable[table] + offset, &pdte, 8);
             base += pageSize;
         }