diff options
author | Min Kyu Jeong <minkyu.jeong@arm.com> | 2010-08-23 11:18:40 -0500 |
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committer | Min Kyu Jeong <minkyu.jeong@arm.com> | 2010-08-23 11:18:40 -0500 |
commit | 5f91ec3f4618dad8d36efbf8b5a5112a1ce0d1b7 (patch) | |
tree | 3984b0d3f3328901bf8c999b9d01162943fb328d /src/arch | |
parent | 7acf67971cca761efec79a0a0ac453b1115387a9 (diff) | |
download | gem5-5f91ec3f4618dad8d36efbf8b5a5112a1ce0d1b7.tar.xz |
ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate.
THis allows the CPU to handle predicated-false instructions accordingly.
This particular patch makes loads that are predicated-false to be sent
straight to the commit stage directly, not waiting for return of the data
that was never requested since it was predicated-false.
Diffstat (limited to 'src/arch')
-rw-r--r-- | src/arch/arm/isa/templates/mem.isa | 21 | ||||
-rw-r--r-- | src/arch/arm/isa/templates/pred.isa | 2 |
2 files changed, 21 insertions, 2 deletions
diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa index ea66ce2a6..5431777b2 100644 --- a/src/arch/arm/isa/templates/mem.isa +++ b/src/arch/arm/isa/templates/mem.isa @@ -69,6 +69,8 @@ def template SwapExecute {{ if (fault == NoFault) { %(op_wb)s; } + } else { + xc->setPredicate(false); } if (fault == NoFault && machInst.itstateMask != 0) { @@ -103,6 +105,8 @@ def template SwapInitiateAcc {{ if (fault == NoFault) { %(op_wb)s; } + } else { + xc->setPredicate(false); } if (fault == NoFault && machInst.itstateMask != 0) { @@ -164,6 +168,8 @@ def template LoadExecute {{ if (fault == NoFault) { %(op_wb)s; } + } else { + xc->setPredicate(false); } if (fault == NoFault && machInst.itstateMask != 0) { @@ -200,6 +206,8 @@ def template StoreExecute {{ if (fault == NoFault) { %(op_wb)s; } + } else { + xc->setPredicate(false); } if (fault == NoFault && machInst.itstateMask != 0) { @@ -242,6 +250,8 @@ def template StoreExExecute {{ if (fault == NoFault) { %(op_wb)s; } + } else { + xc->setPredicate(false); } if (fault == NoFault && machInst.itstateMask != 0) { @@ -279,6 +289,8 @@ def template StoreExInitiateAcc {{ if (fault == NoFault) { %(op_wb)s; } + } else { + xc->setPredicate(false); } if (fault == NoFault && machInst.itstateMask != 0) { @@ -316,6 +328,8 @@ def template StoreInitiateAcc {{ if (fault == NoFault) { %(op_wb)s; } + } else { + xc->setPredicate(false); } if (fault == NoFault && machInst.itstateMask != 0) { @@ -342,8 +356,11 @@ def template LoadInitiateAcc {{ if (fault == NoFault) { fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); } - } else if (fault == NoFault && machInst.itstateMask != 0) { - xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); + } else { + xc->setPredicate(false); + if (fault == NoFault && machInst.itstateMask != 0) { + xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); + } } return fault; diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa index 7a5b92760..1029cfaee 100644 --- a/src/arch/arm/isa/templates/pred.isa +++ b/src/arch/arm/isa/templates/pred.isa @@ -142,6 +142,8 @@ def template PredOpExecute {{ { %(op_wb)s; } + } else { + xc->setPredicate(false); } if (fault == NoFault && machInst.itstateMask != 0) { |