diff options
author | Chun-Chen TK Hsu <chunchenhsu@google.com> | 2019-10-01 21:22:27 +0800 |
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committer | Chun-Chen TK Hsu <chunchenhsu@google.com> | 2019-11-14 00:04:20 +0000 |
commit | 7f25332af078d0843b8f9e343def59c22d12c6a0 (patch) | |
tree | 8ee22c7fefd9a5e54c0dabd807739ed5d5b7b78d /src/arch | |
parent | c2f2913ff23505ceba82f8e5f044ce032455765b (diff) | |
download | gem5-7f25332af078d0843b8f9e343def59c22d12c6a0.tar.xz |
arch-arm: Refactor code to check if gic is GicV2
Refactor code to use cpu_addr only when gic is GicV2 since cpu_addr is
only meanful to GicV2.
Test: Boot Android P successfully with the following command:
M5_PATH=$PWD/fs_files ./build/ARM/gem5.opt
./configs/example/arm/fs_bigLITTLE.py --dtb
$PWD/fs_files/binaries/armv8_gem5_v2_1cpu.dtb --kernel
$PWD/fs_files/binaries/vmlinux --disk $PWD/fs_files/disks/disk.img
--kernel-init "/init" --cpu-type fastmodel --machine-type
VExpressFastmodel --big-cpu-clock "2GHz" --big-cpus 1 --little-cpus 0
--mem-size 8GB --kernel-cmd "earlyprintk=pl011,0x1c090000
console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=8GB
root=/dev/vda1 init=/init androidboot.hardware=gem5 qemu=1 qemu.gles=2
android.bootanim=0 vmalloc=640MB android.early.fstab=/fstab.gem5
androidboot.selinux=permissive audit=0 cma=128M"
Change-Id: Iedd1388f292685c25f1effcd2e14b3db8899dff9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21339
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Diffstat (limited to 'src/arch')
-rw-r--r-- | src/arch/arm/fastmodel/GIC/gic.cc | 12 | ||||
-rw-r--r-- | src/arch/arm/fastmodel/GIC/gic.hh | 8 | ||||
-rw-r--r-- | src/arch/arm/system.cc | 9 |
3 files changed, 24 insertions, 5 deletions
diff --git a/src/arch/arm/fastmodel/GIC/gic.cc b/src/arch/arm/fastmodel/GIC/gic.cc index cb7752892..8a7eb3b62 100644 --- a/src/arch/arm/fastmodel/GIC/gic.cc +++ b/src/arch/arm/fastmodel/GIC/gic.cc @@ -70,7 +70,8 @@ SCGIC::Terminator::sendTowardsCPU(uint8_t len, const uint8_t *data) } SCGIC::SCGIC(const SCFastModelGICParams ¶ms, - sc_core::sc_module_name _name) : scx_evs_GIC(_name) + sc_core::sc_module_name _name) + : scx_evs_GIC(_name), _params(params) { signalInterrupt.bind(signal_interrupt); @@ -349,6 +350,15 @@ GIC::clearPPInt(uint32_t num, uint32_t cpu) scGIC->signalInterrupt->ppi(cpu, num, false); } +bool +GIC::supportsVersion(GicVersion version) +{ + if (scGIC->params().gicv2_only) + return version == GicVersion::GIC_V2; + return (version == GicVersion::GIC_V3) || + (version == GicVersion::GIC_V4 && scGIC->params().has_gicv4_1); +} + } // namespace FastModel FastModel::SCGIC * diff --git a/src/arch/arm/fastmodel/GIC/gic.hh b/src/arch/arm/fastmodel/GIC/gic.hh index aadfa3aea..f607d2b3c 100644 --- a/src/arch/arm/fastmodel/GIC/gic.hh +++ b/src/arch/arm/fastmodel/GIC/gic.hh @@ -79,6 +79,7 @@ class SCGIC : public scx_evs_GIC }; std::unique_ptr<Terminator> terminator; + const SCFastModelGICParams &_params; public: SCGIC(const SCFastModelGICParams ¶ms, sc_core::sc_module_name _name); @@ -94,6 +95,11 @@ class SCGIC : public scx_evs_GIC scx_evs_GIC::start_of_simulation(); } void start_of_simulation() override {} + const SCFastModelGICParams & + params() + { + return _params; + } }; // This class pairs with the one above to implement the receiving end of gem5's @@ -125,6 +131,8 @@ class GIC : public BaseGic void sendPPInt(uint32_t num, uint32_t cpu) override; void clearPPInt(uint32_t num, uint32_t cpu) override; + bool supportsVersion(GicVersion version) override; + AddrRangeList getAddrRanges() const override { return AddrRangeList(); } Tick read(PacketPtr pkt) override { return 0; } Tick write(PacketPtr pkt) override { return 0; } diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc index 6add9c065..c3c2b8d48 100644 --- a/src/arch/arm/system.cc +++ b/src/arch/arm/system.cc @@ -48,7 +48,7 @@ #include "base/loader/object_file.hh" #include "base/loader/symtab.hh" #include "cpu/thread_context.hh" -#include "dev/arm/gic_v3.hh" +#include "dev/arm/gic_v2.hh" #include "mem/fs_translating_port_proxy.hh" #include "mem/physical.hh" #include "sim/full_system.hh" @@ -142,7 +142,8 @@ ArmSystem::initState() const Params* p = params(); if (bootldr) { - bool isGICv3System = dynamic_cast<Gicv3 *>(getGIC()) != nullptr; + bool is_gic_v2 = + getGIC()->supportsVersion(BaseGic::GicVersion::GIC_V2); bootldr->buildImage().write(physProxy); inform("Using bootloader at address %#x\n", bootldr->entryPoint()); @@ -153,14 +154,14 @@ ArmSystem::initState() if (!p->flags_addr) fatal("flags_addr must be set with bootloader\n"); - if (!p->gic_cpu_addr && !isGICv3System) + if (!p->gic_cpu_addr && is_gic_v2) fatal("gic_cpu_addr must be set with bootloader\n"); for (int i = 0; i < threadContexts.size(); i++) { if (!_highestELIs64) threadContexts[i]->setIntReg(3, (kernelEntry & loadAddrMask) + loadAddrOffset); - if (!isGICv3System) + if (is_gic_v2) threadContexts[i]->setIntReg(4, params()->gic_cpu_addr); threadContexts[i]->setIntReg(5, params()->flags_addr); } |