diff options
author | Ali Saidi <saidi@eecs.umich.edu> | 2006-12-09 18:00:40 -0500 |
---|---|---|
committer | Ali Saidi <saidi@eecs.umich.edu> | 2006-12-09 18:00:40 -0500 |
commit | 81a00fdcfef4ecffd57a909db67ca0ff3b99de3a (patch) | |
tree | a80cc38ae0827b41f66560750606bb9061955481 /src/arch | |
parent | ed22eb781dc7714c1b2ca17cf17824917e38319c (diff) | |
download | gem5-81a00fdcfef4ecffd57a909db67ca0ff3b99de3a.tar.xz |
Allocate the correct number of global registers
Fix fault formating and code for traps
fix a couple of bugs in the decoder
Cleanup/fix page table entry code
Implement more mmaped iprs, fix numbered tlb insertion code, add function to dump tlb contents
Don't panic if we differ from legion on a tcc instruction because of where legion prints its data and where we print our data
src/arch/sparc/faults.cc:
Fix fault formating and code for traps
src/arch/sparc/intregfile.hh:
allocate the correct number of global registers
src/arch/sparc/isa/decoder.isa:
fix a couple of bugs in the decoder: wrasi should write asi not ccr, done/retry should get hpstate from htstate
src/arch/sparc/pagetable.hh:
cleanup/fix page table code
src/arch/sparc/tlb.cc:
implement more mmaped iprs, fix numbered insertion code, add function to dump tlb contents
src/arch/sparc/tlb.hh:
add functions to write TagAccess register on tlb miss and to dump all tlb entries for debugging
src/cpu/exetrace.cc:
dump tlb entries on error, don't consider differences the cycle we take a trap to be bad.
--HG--
extra : convert_revision : d7d771900f6f25219f3dc6a6e51986d342a32e03
Diffstat (limited to 'src/arch')
-rw-r--r-- | src/arch/sparc/faults.cc | 20 | ||||
-rw-r--r-- | src/arch/sparc/intregfile.hh | 2 | ||||
-rw-r--r-- | src/arch/sparc/isa/decoder.isa | 3 | ||||
-rw-r--r-- | src/arch/sparc/pagetable.hh | 65 | ||||
-rw-r--r-- | src/arch/sparc/tlb.cc | 175 | ||||
-rw-r--r-- | src/arch/sparc/tlb.hh | 10 |
6 files changed, 188 insertions, 87 deletions
diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc index 78b2b4b76..64cfc832a 100644 --- a/src/arch/sparc/faults.cc +++ b/src/arch/sparc/faults.cc @@ -551,34 +551,26 @@ void SparcFaultBase::invoke(ThreadContext * tc) PrivilegeLevel level = getNextLevel(current); - if(HPSTATE & (1 << 5) || TL == MaxTL - 1) - { + if(HPSTATE & (1 << 5) || TL == MaxTL - 1) { getREDVector(5, PC, NPC); doREDFault(tc, TT); //This changes the hpstate and pstate, so we need to make sure we //save the old version on the trap stack in doREDFault. enterREDState(tc); - } - else if(TL == MaxTL) - { + } else if(TL == MaxTL) { panic("Should go to error state here.. crap\n"); //Do error_state somehow? //Probably inject a WDR fault using the interrupt mechanism. //What should the PC and NPC be set to? - } - else if(TL > MaxPTL && level == Privileged) - { + } else if(TL > MaxPTL && level == Privileged) { //guest_watchdog fault doNormalFault(tc, trapType(), true); getHyperVector(tc, PC, NPC, 2); - } - else if(level == Hyperprivileged) - { + } else if(level == Hyperprivileged || + level == Privileged && trapType() >= 384) { doNormalFault(tc, trapType(), true); getHyperVector(tc, PC, NPC, trapType()); - } - else - { + } else { doNormalFault(tc, trapType(), false); getPrivVector(tc, PC, NPC, trapType(), TL+1); } diff --git a/src/arch/sparc/intregfile.hh b/src/arch/sparc/intregfile.hh index 59f767e8e..d66d0fcb7 100644 --- a/src/arch/sparc/intregfile.hh +++ b/src/arch/sparc/intregfile.hh @@ -67,7 +67,7 @@ namespace SparcISA (unsigned int)(-1) : (1 << FrameOffsetBits) - 1; - IntReg regGlobals[MaxGL][RegsPerFrame]; + IntReg regGlobals[MaxGL+1][RegsPerFrame]; IntReg regSegments[2 * NWindows][RegsPerFrame]; IntReg microRegs[NumMicroIntRegs]; diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index b893797b0..7a48042c2 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -526,7 +526,7 @@ decode OP default Unknown::unknown() 0x00: NoPriv::wry({{Y = Rs1 ^ Rs2_or_imm13;}}); //0x01 should cause an illegal instruction exception 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}}); - 0x03: NoPriv::wrasi({{Ccr = Rs1 ^ Rs2_or_imm13;}}); + 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}}); //0x04-0x05 should cause an illegal instruction exception 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}}); //0x07-0x0E should cause an illegal instruction exception @@ -1017,6 +1017,7 @@ decode OP default Unknown::unknown() Asi = Tstate<31:24>; Ccr = Tstate<39:32>; Gl = Tstate<42:40>; + Hpstate = Htstate; NPC = Tpc; NNPC = Tnpc; Tl = Tl - 1; diff --git a/src/arch/sparc/pagetable.hh b/src/arch/sparc/pagetable.hh index 2e27258a4..fc01e82da 100644 --- a/src/arch/sparc/pagetable.hh +++ b/src/arch/sparc/pagetable.hh @@ -32,6 +32,7 @@ #define __ARCH_SPARC_PAGETABLE_HH__ #include "arch/sparc/isa_traits.hh" +#include "base/bitfield.hh" #include "base/misc.hh" #include "config/full_system.hh" @@ -80,20 +81,19 @@ class PageTableEntry if (type == sun4u) entry4u = entry; else { - uint64_t entry4u = 0; - entry4u |= entry & ULL(0x8000000000000000); //valid - entry4u |= (entry & 0x3) << 61; //size[1:0] - entry4u |= (entry & ULL(0x4000000000000000)) >> 2; //nfo - entry4u |= (entry & 0x1000) << 47; //ie - //entry4u |= (entry & 0x3F00000000000000) >> 7; //soft2 - entry4u |= (entry & 0x4) << 48; //size[2] - //diag? - entry4u |= (entry & ULL(0x0000FFFFFFFFE000)); //paddr - entry4u |= (entry & 0x400) >> 5; //cp - entry4u |= (entry & 0x200) >> 5; //cv - entry4u |= (entry & 0x800) >> 8; //e - entry4u |= (entry & 0x100) >> 6; //p - entry4u |= (entry & 0x40) >> 5; //w + entry4u = 0; + entry4u |= mbits(entry,63,63); //valid + entry4u |= bits(entry,1,0) << 61; //size[1:0] + entry4u |= bits(entry,62,62) << 60; //nfo + entry4u |= bits(entry,12,12) << 59; //ie + entry4u |= bits(entry,2,2) << 48; //size[2] + entry4u |= mbits(entry,39,13); //paddr + entry4u |= bits(entry,61,61) << 6;; // locked + entry4u |= bits(entry,10,10) << 5; //cp + entry4u |= bits(entry,9,9) << 4; //cv + entry4u |= bits(entry,11,11) << 3; //e + entry4u |= bits(entry,8,8) << 2; //p + entry4u |= bits(entry,6,6) << 1; //w } } @@ -112,30 +112,21 @@ class PageTableEntry const PageTableEntry &operator=(const PageTableEntry &e) { populated = true; entry4u = e.entry4u; return *this; } - bool valid() const { return entry4u & ULL(0x8000000000000000) && populated; } + bool valid() const { return bits(entry4u,63,63) && populated; } uint8_t _size() const { assert(populated); - return ((entry4u & 0x6) >> 61) | - ((entry4u & ULL(0x000080000000000)) >> 46); } - Addr size() const { return pageSizes[_size()]; } - bool ie() const { return entry4u >> 59 & 0x1; } - Addr pfn() const { assert(populated); - return entry4u >> 13 & ULL(0xFFFFFFFFFF); } - Addr paddr() const { assert(populated); - return entry4u & ULL(0x0000FFFFFFFFE000); } - bool locked() const { assert(populated); - return entry4u & 0x40; } - bool cv() const { assert(populated); - return entry4u & 0x10; } - bool cp() const { assert(populated); - return entry4u & 0x20; } - bool priv() const { assert(populated); - return entry4u & 0x4; } - bool writable() const { assert(populated); - return entry4u & 0x2; } - bool nofault() const { assert(populated); - return entry4u & ULL(0x1000000000000000); } - bool sideffect() const { assert(populated); - return entry4u & 0x8; } + return bits(entry4u, 62,61) | + bits(entry4u, 48,48) << 2; } + Addr size() const { assert(_size() < 6); return pageSizes[_size()]; } + bool ie() const { return bits(entry4u, 59,59); } + Addr pfn() const { assert(populated); return bits(entry4u,39,13); } + Addr paddr() const { assert(populated); return mbits(entry4u, 39,13);} + bool locked() const { assert(populated); return bits(entry4u,6,6); } + bool cv() const { assert(populated); return bits(entry4u,4,4); } + bool cp() const { assert(populated); return bits(entry4u,5,5); } + bool priv() const { assert(populated); return bits(entry4u,2,2); } + bool writable() const { assert(populated); return bits(entry4u,1,1); } + bool nofault() const { assert(populated); return bits(entry4u,60,60); } + bool sideffect() const { assert(populated); return bits(entry4u,3,3); } }; struct TlbRange { diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index c05434797..b0fc562ac 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -71,27 +71,32 @@ TLB::clearUsedBits() void TLB::insert(Addr va, int partition_id, int context_id, bool real, - const PageTableEntry& PTE) + const PageTableEntry& PTE, int entry) { MapIter i; - TlbEntry *new_entry; + TlbEntry *new_entry = NULL; + int x; - DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x, pid=%d cid=%d r=%d\n", - va, partition_id, context_id, (int)real); + DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d\n", + va, PTE.paddr(), partition_id, context_id, (int)real); - int x = -1; - for (x = 0; x < size; x++) { - if (!tlb[x].valid || !tlb[x].used) { - new_entry = &tlb[x]; - break; + if (entry != -1) { + assert(entry < size && entry >= 0); + new_entry = &tlb[entry]; + } else { + for (x = 0; x < size; x++) { + if (!tlb[x].valid || !tlb[x].used) { + new_entry = &tlb[x]; + break; + } } } // Update the last ently if their all locked - if (x == -1) - x = size - 1; + if (!new_entry) + new_entry = &tlb[size-1]; assert(PTE.valid()); new_entry->range.va = va; @@ -152,10 +157,11 @@ TLB::lookup(Addr va, int partition_id, bool real, int context_id) DPRINTF(TLB, "TLB: No valid entry found\n"); return NULL; } - DPRINTF(TLB, "TLB: Valid entry found\n"); // Mark the entries used bit and clear other used bits in needed t = i->second; + DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(), + t->pte.size()); if (!t->used) { t->used = true; usedEntries++; @@ -169,6 +175,18 @@ TLB::lookup(Addr va, int partition_id, bool real, int context_id) return t; } +void +TLB::dumpAll() +{ + for (int x = 0; x < size; x++) { + if (tlb[x].valid) { + DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n", + x, tlb[x].range.partitionId, tlb[x].range.contextId, + tlb[x].range.real ? 'R' : ' ', tlb[x].range.size, + tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte()); + } + } +} void TLB::demapPage(Addr va, int partition_id, bool real, int context_id) @@ -285,9 +303,14 @@ TLB::writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct, sfsr |= 1 << 6; sfsr |= ft << 7; sfsr |= asi << 16; - tc->setMiscReg(reg, sfsr); + tc->setMiscRegWithEffect(reg, sfsr); } +void +TLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context) +{ + tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0)); +} void ITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct, @@ -299,16 +322,29 @@ ITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct, } void +ITB::writeTagAccess(ThreadContext *tc, Addr va, int context) +{ + TLB::writeTagAccess(tc, MISCREG_MMU_ITLB_TAG_ACCESS, va, context); +} + +void DTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct, bool se, FaultTypes ft, int asi) { DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", a, (int)write, ct, ft, asi); TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi); - tc->setMiscReg(MISCREG_MMU_DTLB_SFAR, a); + tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR, a); +} + + void +DTB::writeTagAccess(ThreadContext *tc, Addr va, int context) +{ + TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context); } + Fault ITB::translate(RequestPtr &req, ThreadContext *tc) { @@ -349,7 +385,7 @@ ITB::translate(RequestPtr &req, ThreadContext *tc) } // If the asi is unaligned trap - if (vaddr & 0x7) { + if (vaddr & req->getSize()-1) { writeSfsr(tc, false, ct, false, OtherFault, asi); return new MemAddressNotAligned; } @@ -385,8 +421,9 @@ ITB::translate(RequestPtr &req, ThreadContext *tc) return new InstructionAccessException; } - req->setPaddr(e->pte.paddr() & ~e->pte.size() | - req->getVaddr() & e->pte.size()); + req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | + req->getVaddr() & e->pte.size()-1 ); + DPRINTF(TLB, "TLB: %#X -> %#X\n", req->getVaddr(), req->getPaddr()); return NoFault; } @@ -456,20 +493,12 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) return new DataAccessException; } - } - - // If the asi is unaligned trap - if (vaddr & size-1) { - writeSfr(tc, vaddr, false, ct, false, OtherFault, asi); - return new MemAddressNotAligned; - } - - if (addr_mask) - vaddr = vaddr & VAddrAMask; - - if (!validVirtualAddress(vaddr, addr_mask)) { - writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi); - return new DataAccessException; + } else if (hpriv) { + if (asi == ASI_P) { + ct = Primary; + context = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); + goto continueDtbFlow; + } } if (!implicit) { @@ -499,6 +528,22 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) panic("Accessing ASI %#X. Should we?\n", asi); } +continueDtbFlow: + // If the asi is unaligned trap + if (vaddr & size-1) { + writeSfr(tc, vaddr, false, ct, false, OtherFault, asi); + return new MemAddressNotAligned; + } + + if (addr_mask) + vaddr = vaddr & VAddrAMask; + + if (!validVirtualAddress(vaddr, addr_mask)) { + writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi); + return new DataAccessException; + } + + if ((!lsuDm && !hpriv) || AsiIsReal(asi)) { real = true; context = 0; @@ -542,8 +587,9 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) return new DataAccessException; } - req->setPaddr(e->pte.paddr() & ~e->pte.size() | - req->getVaddr() & e->pte.size()); + req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | + req->getVaddr() & e->pte.size()-1); + DPRINTF(TLB, "TLB: %#X -> %#X\n", req->getVaddr(), req->getPaddr()); return NoFault; /** Normal flow ends here. */ @@ -664,12 +710,28 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) assert(va == 0); pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG)); break; + case ASI_SPARC_ERROR_STATUS_REG: + warn("returning 0 for SPARC ERROR regsiter read\n"); + pkt->set(0); + break; case ASI_HYP_SCRATCHPAD: case ASI_SCRATCHPAD: pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3))); break; + case ASI_IMMU: + switch (va) { + case 0x30: + pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS)); + break; + default: + goto doMmuReadError; + } + break; case ASI_DMMU: switch (va) { + case 0x30: + pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS)); + break; case 0x80: pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID)); break; @@ -693,6 +755,14 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) Addr va = pkt->getAddr(); ASI asi = (ASI)pkt->req->getAsi(); + Addr ta_insert; + Addr va_insert; + Addr ct_insert; + int part_insert; + int entry_insert = -1; + bool real_insert; + PageTableEntry pte; + DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n", (uint32_t)asi, va, data); @@ -774,8 +844,47 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) case ASI_SCRATCHPAD: tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); break; + case ASI_IMMU: + switch (va) { + case 0x30: + tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data); + break; + default: + goto doMmuWriteError; + } + break; + case ASI_ITLB_DATA_ACCESS_REG: + entry_insert = bits(va, 8,3); + case ASI_ITLB_DATA_IN_REG: + assert(entry_insert != -1 || mbits(va,10,9) == va); + ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); + va_insert = mbits(ta_insert, 63,13); + ct_insert = mbits(ta_insert, 12,0); + part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); + real_insert = bits(va, 9,9); + pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : + PageTableEntry::sun4u); + tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert, + pte, entry_insert); + break; + case ASI_DTLB_DATA_ACCESS_REG: + entry_insert = bits(va, 8,3); + case ASI_DTLB_DATA_IN_REG: + assert(entry_insert != -1 || mbits(va,10,9) == va); + ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); + va_insert = mbits(ta_insert, 63,13); + ct_insert = mbits(ta_insert, 12,0); + part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); + real_insert = bits(va, 9,9); + pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : + PageTableEntry::sun4u); + insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert); + break; case ASI_DMMU: switch (va) { + case 0x30: + tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data); + break; case 0x80: tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data); break; diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh index 2df4fe4c8..8a4ccd69f 100644 --- a/src/arch/sparc/tlb.hh +++ b/src/arch/sparc/tlb.hh @@ -84,7 +84,7 @@ class TLB : public SimObject /** Insert a PTE into the TLB. */ void insert(Addr vpn, int partition_id, int context_id, bool real, - const PageTableEntry& PTE); + const PageTableEntry& PTE, int entry = -1); /** Given an entry id, read that tlb entries' tag. */ uint64_t TagRead(int entry); @@ -114,9 +114,13 @@ class TLB : public SimObject void TLB::clearUsedBits(); + void writeTagAccess(ThreadContext *tc, int reg, Addr va, int context); + public: TLB(const std::string &name, int size); + void dumpAll(); + // Checkpointing virtual void serialize(std::ostream &os); virtual void unserialize(Checkpoint *cp, const std::string §ion); @@ -133,6 +137,8 @@ class ITB : public TLB private: void writeSfsr(ThreadContext *tc, bool write, ContextType ct, bool se, FaultTypes ft, int asi); + void writeTagAccess(ThreadContext *tc, Addr va, int context); + friend class DTB; }; class DTB : public TLB @@ -149,6 +155,8 @@ class DTB : public TLB private: void writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct, bool se, FaultTypes ft, int asi); + void writeTagAccess(ThreadContext *tc, Addr va, int context); + }; |