arch,cpu: Move endianness conversion of inst bytes into the ISA.

It doesn't matter if the bytes are converted before or after they're
fed into the decoder. The ISA already knows what endianness to use
implicitly, and this frees the CPU which doesn't from having to worry
about it.

Change-Id: Id6574ee81bbf4f032c1d7b2901a664f2bd014fbc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22343
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

7 files changed, 7 insertions, 6 deletions

diff --git a/src/arch/alpha/decoder.hh b/src/arch/alpha/decoder.hh
index 522359c28..0ee425077 100644
--- a/src/arch/alpha/decoder.hh
+++ b/src/arch/alpha/decoder.hh
@@ -66,7 +66,7 @@ class Decoder
     void
     moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
     {
-        ext_inst = inst;
+        ext_inst = letoh(inst);
         instDone = true;
         if (FullSystem)
             ext_inst |= (static_cast<ExtMachInst>(pc.pc() & 0x1) << 32);
diff --git a/src/arch/arm/decoder.cc b/src/arch/arm/decoder.cc
index 4c86ee2c6..a2c504334 100644
--- a/src/arch/arm/decoder.cc
+++ b/src/arch/arm/decoder.cc
@@ -154,7 +154,7 @@ Decoder::consumeBytes(int numBytes)
 void
 Decoder::moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
 {
-    data = inst;
+    data = letoh(inst);
     offset = (fetchPC >= pc.instAddr()) ? 0 : pc.instAddr() - fetchPC;
     emi.thumb = pc.thumb();
     emi.aarch64 = pc.aarch64();
diff --git a/src/arch/mips/decoder.hh b/src/arch/mips/decoder.hh
index 4a2fc46a5..825ab8ada 100644
--- a/src/arch/mips/decoder.hh
+++ b/src/arch/mips/decoder.hh
@@ -68,7 +68,7 @@ class Decoder
     void
     moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
     {
-        emi = inst;
+        emi = letoh(inst);
         instDone = true;
     }
 
diff --git a/src/arch/power/decoder.hh b/src/arch/power/decoder.hh
index cc086adc5..56273f8db 100644
--- a/src/arch/power/decoder.hh
+++ b/src/arch/power/decoder.hh
@@ -67,7 +67,7 @@ class Decoder
     void
     moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
     {
-        emi = inst;
+        emi = betoh(inst);
         instDone = true;
     }
 
diff --git a/src/arch/riscv/decoder.cc b/src/arch/riscv/decoder.cc
index 41a52020e..69c392194 100644
--- a/src/arch/riscv/decoder.cc
+++ b/src/arch/riscv/decoder.cc
@@ -52,6 +52,7 @@ void Decoder::reset()
 void
 Decoder::moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
 {
+    inst = letoh(inst);
     DPRINTF(Decode, "Requesting bytes 0x%08x from address %#x\n", inst,
             fetchPC);
 
diff --git a/src/arch/sparc/decoder.hh b/src/arch/sparc/decoder.hh
index 6fa506f37..8124a6963 100644
--- a/src/arch/sparc/decoder.hh
+++ b/src/arch/sparc/decoder.hh
@@ -65,7 +65,7 @@ class Decoder
     void
     moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
     {
-        emi = inst;
+        emi = betoh(inst);
         // The I bit, bit 13, is used to figure out where the ASI
         // should come from. Use that in the ExtMachInst. This is
         // slightly redundant, but it removes the need to put a condition
diff --git a/src/arch/x86/decoder.hh b/src/arch/x86/decoder.hh
index 412b7c73f..064fd3a80 100644
--- a/src/arch/x86/decoder.hh
+++ b/src/arch/x86/decoder.hh
@@ -310,7 +310,7 @@ class Decoder
         DPRINTF(Decoder, "Getting more bytes.\n");
         basePC = fetchPC;
         offset = (fetchPC >= pc.instAddr()) ? 0 : pc.instAddr() - fetchPC;
-        fetchChunk = data;
+        fetchChunk = letoh(data);
         outOfBytes = false;
         process();
     }