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author | Gabe Black <gblack@eecs.umich.edu> | 2010-08-23 16:14:20 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2010-08-23 16:14:20 -0700 |
commit | 943c1714803bb87d3b05b2516701dfb792996805 (patch) | |
tree | cfefb1ef949355bc237c9b6e37117b9b059e0116 /src/arch | |
parent | 9581562e653f6df810e40c076bc97d50daccf302 (diff) | |
download | gem5-943c1714803bb87d3b05b2516701dfb792996805.tar.xz |
ISA: Get rid of old, unused utility functions cluttering up the ISAs.
Diffstat (limited to 'src/arch')
-rw-r--r-- | src/arch/alpha/ev5.cc | 47 | ||||
-rw-r--r-- | src/arch/alpha/utility.hh | 69 | ||||
-rw-r--r-- | src/arch/arm/utility.hh | 19 | ||||
-rwxr-xr-x | src/arch/mips/mips_core_specific.cc | 5 | ||||
-rw-r--r-- | src/arch/mips/mips_core_specific.hh | 7 | ||||
-rw-r--r-- | src/arch/mips/utility.hh | 24 | ||||
-rw-r--r-- | src/arch/power/utility.hh | 27 | ||||
-rw-r--r-- | src/arch/sparc/utility.hh | 38 | ||||
-rw-r--r-- | src/arch/x86/utility.hh | 38 |
9 files changed, 0 insertions, 274 deletions
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc index 609b45957..0db75df46 100644 --- a/src/arch/alpha/ev5.cc +++ b/src/arch/alpha/ev5.cc @@ -66,53 +66,6 @@ initCPU(ThreadContext *tc, int cpuId) delete reset; } - -template <class CPU> -void -processInterrupts(CPU *cpu) -{ - //Check if there are any outstanding interrupts - //Handle the interrupts - int ipl = 0; - int summary = 0; - - if (cpu->readMiscRegNoEffect(IPR_ASTRR)) - panic("asynchronous traps not implemented\n"); - - if (cpu->readMiscRegNoEffect(IPR_SIRR)) { - for (int i = INTLEVEL_SOFTWARE_MIN; - i < INTLEVEL_SOFTWARE_MAX; i++) { - if (cpu->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) { - // See table 4-19 of the 21164 hardware reference - ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; - summary |= (ULL(1) << i); - } - } - } - - uint64_t interrupts = cpu->intr_status(); - - if (interrupts) { - for (int i = INTLEVEL_EXTERNAL_MIN; - i < INTLEVEL_EXTERNAL_MAX; i++) { - if (interrupts & (ULL(1) << i)) { - // See table 4-19 of the 21164 hardware reference - ipl = i; - summary |= (ULL(1) << i); - } - } - } - - if (ipl && ipl > cpu->readMiscRegNoEffect(IPR_IPLR)) { - cpu->setMiscRegNoEffect(IPR_ISR, summary); - cpu->setMiscRegNoEffect(IPR_INTID, ipl); - cpu->trap(new InterruptFault); - DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", - cpu->readMiscRegNoEffect(IPR_IPLR), ipl, summary); - } - -} - template <class CPU> void zeroRegisters(CPU *cpu) diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh index 0b994d324..281fc4492 100644 --- a/src/arch/alpha/utility.hh +++ b/src/arch/alpha/utility.hh @@ -49,68 +49,6 @@ inUserMode(ThreadContext *tc) return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0; } -inline bool -isCallerSaveIntegerRegister(unsigned int reg) -{ - panic("register classification not implemented"); - return (reg >= 1 && reg <= 8) || (reg >= 22 && reg <= 25) || reg == 27; -} - -inline bool -isCalleeSaveIntegerRegister(unsigned int reg) -{ - panic("register classification not implemented"); - return reg >= 9 && reg <= 15; -} - -inline bool -isCallerSaveFloatRegister(unsigned int reg) -{ - panic("register classification not implemented"); - return false; -} - -inline bool -isCalleeSaveFloatRegister(unsigned int reg) -{ - panic("register classification not implemented"); - return false; -} - -inline Addr -alignAddress(const Addr &addr, unsigned int nbytes) -{ - return (addr & ~(nbytes - 1)); -} - -// Instruction address compression hooks -inline Addr -realPCToFetchPC(const Addr &addr) -{ - return addr; -} - -inline Addr -fetchPCToRealPC(const Addr &addr) -{ - return addr; -} - -// the size of "fetched" instructions (not necessarily the size -// of real instructions for PISA) -inline size_t -fetchInstSize() -{ - return sizeof(MachInst); -} - -inline MachInst -makeRegisterCopy(int dest, int src) -{ - panic("makeRegisterCopy not implemented"); - return 0; -} - /** * Function to insure ISA semantics about 0 registers. * @param tc The thread context. @@ -150,13 +88,6 @@ RoundPage(Addr addr) void initIPRs(ThreadContext *tc, int cpuId); #if FULL_SYSTEM void initCPU(ThreadContext *tc, int cpuId); - -/** - * Function to check for and process any interrupts. - * @param tc The thread context. - */ -template <class TC> -void processInterrupts(TC *tc); #endif void copyRegs(ThreadContext *src, ThreadContext *dest); diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh index 6ee2fb325..076468e0d 100644 --- a/src/arch/arm/utility.hh +++ b/src/arch/arm/utility.hh @@ -96,25 +96,6 @@ namespace ArmISA { template <class TC> void zeroRegisters(TC *tc); - // Instruction address compression hooks - static inline Addr realPCToFetchPC(const Addr &addr) { - return addr; - } - - static inline Addr fetchPCToRealPC(const Addr &addr) { - return addr; - } - - // the size of "fetched" instructions - static inline size_t fetchInstSize() { - return sizeof(MachInst); - } - - static inline MachInst makeRegisterCopy(int dest, int src) { - panic("makeRegisterCopy not implemented"); - return 0; - } - inline void startupCPU(ThreadContext *tc, int cpuId) { tc->activate(0); diff --git a/src/arch/mips/mips_core_specific.cc b/src/arch/mips/mips_core_specific.cc index 14f4186e3..31d47c842 100755 --- a/src/arch/mips/mips_core_specific.cc +++ b/src/arch/mips/mips_core_specific.cc @@ -43,9 +43,4 @@ void MipsISA::initCPU(ThreadContext *tc, int cpuId) {} -template <class CPU> -void -MipsISA::processInterrupts(CPU *cpu) -{} - #endif // FULL_SYSTEM || BARE_IRON diff --git a/src/arch/mips/mips_core_specific.hh b/src/arch/mips/mips_core_specific.hh index 0d19bf944..bd66e049f 100644 --- a/src/arch/mips/mips_core_specific.hh +++ b/src/arch/mips/mips_core_specific.hh @@ -37,13 +37,6 @@ class ThreadContext; namespace MipsISA { void initCPU(ThreadContext *tc, int cpuId); - - /** - * Function to check for and process any interrupts. - * @param tc The thread context. - */ - template <class CPU> - void processInterrupts(CPU *cpu); }; #endif // __ARCH_MIPS_CORE_SPECIFIC_HH__ diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh index 1e58238e9..f827e9b33 100644 --- a/src/arch/mips/utility.hh +++ b/src/arch/mips/utility.hh @@ -79,30 +79,6 @@ inUserMode(ThreadContext *tc) } } -// Instruction address compression hooks -static inline Addr realPCToFetchPC(const Addr &addr) { - return addr; -} - -static inline Addr fetchPCToRealPC(const Addr &addr) { - return addr; -} - -// the size of "fetched" instructions (not necessarily the size -// of real instructions for PISA) -static inline size_t fetchInstSize() { - return sizeof(MachInst); -} - -//////////////////////////////////////////////////////////////////////// -// -// Register File Utility Functions -// -static inline MachInst makeRegisterCopy(int dest, int src) { - panic("makeRegisterCopy not implemented"); - return 0; -} - template <class CPU> void zeroRegisters(CPU *cpu); diff --git a/src/arch/power/utility.hh b/src/arch/power/utility.hh index 6263635e9..aff6fda78 100644 --- a/src/arch/power/utility.hh +++ b/src/arch/power/utility.hh @@ -61,33 +61,6 @@ namespace PowerISA { template <class TC> void zeroRegisters(TC *tc); -// Instruction address compression hooks -static inline Addr -realPCToFetchPC(const Addr &addr) -{ - return addr; -} - -static inline Addr -fetchPCToRealPC(const Addr &addr) -{ - return addr; -} - -// the size of "fetched" instructions -static inline size_t -fetchInstSize() -{ - return sizeof(MachInst); -} - -static inline MachInst -makeRegisterCopy(int dest, int src) -{ - panic("makeRegisterCopy not implemented"); - return 0; -} - inline void startupCPU(ThreadContext *tc, int cpuId) { diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh index 064af9c6a..fe3082c5e 100644 --- a/src/arch/sparc/utility.hh +++ b/src/arch/sparc/utility.hh @@ -50,44 +50,6 @@ namespace SparcISA (tc->readMiscRegNoEffect(MISCREG_HPSTATE) & (1 << 2))); } - inline bool isCallerSaveIntegerRegister(unsigned int reg) { - panic("register classification not implemented"); - return false; - } - - inline bool isCalleeSaveIntegerRegister(unsigned int reg) { - panic("register classification not implemented"); - return false; - } - - inline bool isCallerSaveFloatRegister(unsigned int reg) { - panic("register classification not implemented"); - return false; - } - - inline bool isCalleeSaveFloatRegister(unsigned int reg) { - panic("register classification not implemented"); - return false; - } - - // Instruction address compression hooks - inline Addr realPCToFetchPC(const Addr &addr) - { - return addr; - } - - inline Addr fetchPCToRealPC(const Addr &addr) - { - return addr; - } - - // the size of "fetched" instructions (not necessarily the size - // of real instructions for PISA) - inline size_t fetchInstSize() - { - return sizeof(MachInst); - } - /** * Function to insure ISA semantics about 0 registers. * @param tc The thread context. diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh index d83353162..4c987faee 100644 --- a/src/arch/x86/utility.hh +++ b/src/arch/x86/utility.hh @@ -85,44 +85,6 @@ namespace X86ISA #endif } - inline bool isCallerSaveIntegerRegister(unsigned int reg) { - panic("register classification not implemented"); - return false; - } - - inline bool isCalleeSaveIntegerRegister(unsigned int reg) { - panic("register classification not implemented"); - return false; - } - - inline bool isCallerSaveFloatRegister(unsigned int reg) { - panic("register classification not implemented"); - return false; - } - - inline bool isCalleeSaveFloatRegister(unsigned int reg) { - panic("register classification not implemented"); - return false; - } - - // Instruction address compression hooks - inline Addr realPCToFetchPC(const Addr &addr) - { - return addr; - } - - inline Addr fetchPCToRealPC(const Addr &addr) - { - return addr; - } - - // the size of "fetched" instructions (not necessarily the size - // of real instructions for PISA) - inline size_t fetchInstSize() - { - return sizeof(MachInst); - } - /** * Function to insure ISA semantics about 0 registers. * @param tc The thread context. |