SimObjects: Clean up handling of C++ namespaces.

Make them easier to express by only having the cxx_type parameter which
has the full namespace name, and drop the cxx_namespace thing.
Add support for multiple levels of namespace.

5 files changed, 12 insertions, 30 deletions

diff --git a/src/arch/alpha/AlphaTLB.py b/src/arch/alpha/AlphaTLB.py
index fec245b75..7cfb549f3 100644
--- a/src/arch/alpha/AlphaTLB.py
+++ b/src/arch/alpha/AlphaTLB.py
@@ -35,14 +35,10 @@ class AlphaTLB(SimObject):
 
 class AlphaDTB(AlphaTLB):
     type = 'AlphaDTB'
-    cxx_namespace = 'AlphaISA'
-    cxx_class = 'DTB'
-
+    cxx_class = 'AlphaISA::DTB'
     size = 64
 
 class AlphaITB(AlphaTLB):
     type = 'AlphaITB'
-    cxx_namespace = 'AlphaISA'
-    cxx_class = 'ITB'
-
+    cxx_class = 'AlphaISA::ITB'
     size = 48
diff --git a/src/arch/mips/MipsTLB.py b/src/arch/mips/MipsTLB.py
index 1d0244e22..0054acae5 100644
--- a/src/arch/mips/MipsTLB.py
+++ b/src/arch/mips/MipsTLB.py
@@ -39,19 +39,16 @@ class MipsTLB(SimObject):
 
 class MipsDTB(MipsTLB):
     type = 'MipsDTB'
-    cxx_namespace = 'MipsISA'
-    cxx_class = 'DTB'
+    cxx_class = 'MipsISA::DTB'
     size = 64
 
 class MipsITB(MipsTLB):
     type = 'MipsITB'
-    cxx_namespace = 'MipsISA'
-    cxx_class = 'ITB'
+    cxx_class = 'MipsISA::ITB'
     size = 64
 
 class MipsUTB(MipsTLB):
     type = 'MipsUTB'
-    cxx_namespace = 'MipsISA'
-    cxx_class = 'UTB'
+    cxx_class = 'MipsISA::UTB'
     size = 64
 
diff --git a/src/arch/sparc/SparcTLB.py b/src/arch/sparc/SparcTLB.py
index 2d0257cd7..20672a24e 100644
--- a/src/arch/sparc/SparcTLB.py
+++ b/src/arch/sparc/SparcTLB.py
@@ -35,14 +35,10 @@ class SparcTLB(SimObject):
 
 class SparcDTB(SparcTLB):
     type = 'SparcDTB'
-    cxx_namespace = 'SparcISA'
-    cxx_class = 'DTB'
-
+    cxx_class = 'SparcISA::DTB'
     size = 64
 
 class SparcITB(SparcTLB):
     type = 'SparcITB'
-    cxx_namespace = 'SparcISA'
-    cxx_class = 'ITB'
-
+    cxx_class = 'SparcISA::ITB'
     size = 64
diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py
index 8dd53620e..c20566efb 100644
--- a/src/arch/x86/X86TLB.py
+++ b/src/arch/x86/X86TLB.py
@@ -62,8 +62,7 @@ from m5 import build_env
 if build_env['FULL_SYSTEM']:
     class X86PagetableWalker(MemObject):
         type = 'X86PagetableWalker'
-        cxx_namespace = 'X86ISA'
-        cxx_class = 'Walker'
+        cxx_class = 'X86ISA::Walker'
         port = Port("Port for the hardware table walker")
         system = Param.System(Parent.any, "system object")
 
@@ -77,14 +76,10 @@ class X86TLB(SimObject):
 
 class X86DTB(X86TLB):
     type = 'X86DTB'
-    cxx_namespace = 'X86ISA'
-    cxx_class = 'DTB'
-
+    cxx_class = 'X86ISA::DTB'
     size = 64
 
 class X86ITB(X86TLB):
     type = 'X86ITB'
-    cxx_namespace = 'X86ISA'
-    cxx_class = 'ITB'
-
+    cxx_class = 'X86ISA::ITB'
     size = 64
diff --git a/src/arch/x86/bios/E820.py b/src/arch/x86/bios/E820.py
index e161cd56f..288c253fb 100644
--- a/src/arch/x86/bios/E820.py
+++ b/src/arch/x86/bios/E820.py
@@ -58,8 +58,7 @@ from m5.SimObject import SimObject
 
 class X86E820Entry(SimObject):
     type = 'X86E820Entry'
-    cxx_namespace = 'X86ISA'
-    cxx_class = 'E820Entry'
+    cxx_class = 'X86ISA::E820Entry'
 
     addr = Param.Addr(0, 'address of the beginning of the region')
     size = Param.MemorySize('0B', 'size of the region')
@@ -67,7 +66,6 @@ class X86E820Entry(SimObject):
 
 class X86E820Table(SimObject):
     type = 'X86E820Table'
-    cxx_namespace = 'X86ISA'
-    cxx_class = 'E820Table'
+    cxx_class = 'X86ISA::E820Table'
 
     entries = VectorParam.X86E820Entry([], 'entries for the e820 table')