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| author | Javier Setoain <javier.setoain@arm.com> | 2019-03-14 17:42:44 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-03-28 10:28:11 +0000 |
| commit | a93fe3f3cf2b2ad7b0c5b9916bc705a579ca231c (patch) | |
| tree | 3b395f98c47f59dbad26bb0aaafe26ef07d7d55b /src/arch | |
| parent | 93ad0d4324acd674f1877a1146c58412a03b4c39 (diff) | |
| download | gem5-a93fe3f3cf2b2ad7b0c5b9916bc705a579ca231c.tar.xz | |
arch-arm: Fix use of bitwise operators on booleans
Change-Id: I3762b2921f1d00a9104d8dc11a19dc0a219581e5
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17288
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/arm/isa/insts/sve.isa | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa index b1b946f63..647ceafe3 100644 --- a/src/arch/arm/isa/insts/sve.isa +++ b/src/arch/arm/isa/insts/sve.isa @@ -3182,9 +3182,9 @@ let {{ sveBinInst('bic', 'BicPred', 'SimdAluOp', unsignedTypes, bicCode, PredType.MERGE, True) # BIC (vectors, unpredicated) - bicCode = 'destElem = srcElem1 & ~srcElem2;' sveBinInst('bic', 'BicUnpred', 'SimdAluOp', unsignedTypes, bicCode) # BIC, BICS (predicates) + bicCode = 'destElem = srcElem1 && !srcElem2;' svePredLogicalInst('bic', 'PredBic', 'SimdPredAluOp', ('uint8_t',), bicCode) svePredLogicalInst('bics', 'PredBics', 'SimdPredAluOp', ('uint8_t',), |