summaryrefslogtreecommitdiff
path: root/src/arch
diff options
context:
space:
mode:
authorBrandon Potter <brandon.potter@amd.com>2019-10-18 14:43:14 -0400
committerBobby R. Bruce <bbruce@ucdavis.edu>2019-11-20 18:39:09 +0000
commitb4c9996d894118be04cdf4ed793b35a1d5001942 (patch)
treecd3b53dd0d0f6c7cd10c71c72592d6859a33ff1f /src/arch
parent1c4d64fb104245e7e655113155be02a5209e46c0 (diff)
downloadgem5-b4c9996d894118be04cdf4ed793b35a1d5001942.tar.xz
base,tests: Expanded GTests for addr_range.hh
These tests assume the "end address" is not included in the range. This exposed some bugs in addr_range.hh which have been fixed. Where appropriate code comments in addr_range.hh have been extended to improve understanding of the class's behavior. Hard-coded AddrRange values in the project have been updated to take into account that end address is now exclusive. The python params.py interface has been updated to conform to this new standard. Change-Id: Idd1e75d5771d198c4b8142b28de0f3a6e9007a52 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22427 Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/x86/tlb.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 84965b881..2985a8bcb 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -229,7 +229,7 @@ TLB::finalizePhysical(const RequestPtr &req,
{
Addr paddr = req->getPaddr();
- AddrRange m5opRange(0xFFFF0000, 0xFFFFFFFF);
+ AddrRange m5opRange(0xFFFF0000, 0x100000000);
if (m5opRange.contains(paddr)) {
req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR |
@@ -241,7 +241,7 @@ TLB::finalizePhysical(const RequestPtr &req,
LocalApicBase localApicBase =
tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
AddrRange apicRange(localApicBase.base * PageBytes,
- (localApicBase.base + 1) * PageBytes - 1);
+ (localApicBase.base + 1) * PageBytes);
if (apicRange.contains(paddr)) {
// The Intel developer's manuals say the below restrictions apply,