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| author | Tony Gutierrez <anthony.gutierrez@amd.com> | 2019-04-08 12:21:53 -0400 |
|---|---|---|
| committer | Anthony Gutierrez <anthony.gutierrez@amd.com> | 2019-08-09 23:28:54 +0000 |
| commit | c9e0a5f200a023b0687428561fbcefc9332f93c2 (patch) | |
| tree | e4eaaab47a128ca6f8d288fd4756baabe2dcc51e /src/arch | |
| parent | 00001e4d86094f7b7967db99bc45cb8752d2ea95 (diff) | |
| download | gem5-c9e0a5f200a023b0687428561fbcefc9332f93c2.tar.xz | |
arch: Bump MaxVecRegLenInBytes to 4096
The GPU model uses the generic vector register
containers, however the maximum vector register
length is fixed at 256, which is an invalid assumption
for the GPU model as it can operate on vectors up
to 4096B.
Change-Id: Id85e0ed45c9a9c1a4bb6e712c44eaeec2d628fce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17908
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/generic/vec_reg.hh | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/generic/vec_reg.hh b/src/arch/generic/vec_reg.hh index ed2545c64..aab307b42 100644 --- a/src/arch/generic/vec_reg.hh +++ b/src/arch/generic/vec_reg.hh @@ -154,7 +154,7 @@ #include "base/cprintf.hh" #include "base/logging.hh" -constexpr unsigned MaxVecRegLenInBytes = 256; +constexpr unsigned MaxVecRegLenInBytes = 4096; template <size_t Sz> class VecRegContainer; @@ -523,6 +523,7 @@ class VecLaneT friend class VecRegContainer<32>; friend class VecRegContainer<64>; friend class VecRegContainer<128>; + friend class VecRegContainer<256>; friend class VecRegContainer<MaxVecRegLenInBytes>; /** My type alias. */ |