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| author | Andrea Mondelli <Andrea.Mondelli@ucf.edu> | 2019-03-06 10:50:48 -0500 |
|---|---|---|
| committer | Andrea Mondelli <Andrea.Mondelli@ucf.edu> | 2019-04-03 16:50:22 +0000 |
| commit | e13d6dc9c0d7a4ae0215f1ee6793eb32570c5169 (patch) | |
| tree | 460b5ce101d25d9251137506777c3394f8dd805b /src/arch | |
| parent | 5084b90e2af6e5bfad3119b4431a3b063ef3b799 (diff) | |
| download | gem5-e13d6dc9c0d7a4ae0215f1ee6793eb32570c5169.tar.xz | |
misc: Removed inconsistency in O3* debug msgs
Added consistency in the DEBUG message form, to allow a better parsing.
Fixed sn/tid type parameter.
Removed some annoying newlines
Change-Id: I4761c49fc12b874a7d8b46779475b606865cad4b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17248
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/mips/isa.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc index 2711712fe..eaee294c8 100644 --- a/src/arch/mips/isa.cc +++ b/src/arch/mips/isa.cc @@ -450,7 +450,7 @@ ISA::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid) unsigned reg_sel = (bankType[misc_reg] == perThreadContext) ? tid : getVPENum(tid); DPRINTF(MipsPRA, - "[tid:%i]: Setting (direct set) CP0 Register:%u " + "[tid:%i] Setting (direct set) CP0 Register:%u " "Select:%u (%s) to %#x.\n", tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val); @@ -463,7 +463,7 @@ ISA::setRegMask(int misc_reg, RegVal val, ThreadID tid) unsigned reg_sel = (bankType[misc_reg] == perThreadContext) ? tid : getVPENum(tid); DPRINTF(MipsPRA, - "[tid:%i]: Setting CP0 Register: %u Select: %u (%s) to %#x\n", + "[tid:%i] Setting CP0 Register: %u Select: %u (%s) to %#x\n", tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val); miscRegFile_WriteMask[misc_reg][reg_sel] = val; } @@ -479,7 +479,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc, ThreadID tid) ? tid : getVPENum(tid); DPRINTF(MipsPRA, - "[tid:%i]: Setting CP0 Register:%u " + "[tid:%i] Setting CP0 Register:%u " "Select:%u (%s) to %#x, with effect.\n", tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val); |