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| author | Chun-Chen TK Hsu <chunchenhsu@google.com> | 2019-10-08 19:02:33 +0800 |
|---|---|---|
| committer | Chun-Chen TK Hsu <chunchenhsu@google.com> | 2019-10-09 03:45:47 +0000 |
| commit | e1a97946510dd5551f2adf4d7367a954cb34330b (patch) | |
| tree | bb887135f0581a1ea8681c7ebf4e35e2119df317 /src/arch | |
| parent | b1fb2d55c598d89e5a29c569da546b74f99a8bbc (diff) | |
| download | gem5-e1a97946510dd5551f2adf4d7367a954cb34330b.tar.xz | |
system-arm: Initialize ICC_SRE_EL3 register of all CPUs
Fix a bug that only CPU0 initialized ICC_SRE_EL3 register.
Change-Id: I625c9a25bada80b864e5eb5a8b8be14ee324b801
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21539
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Diffstat (limited to 'src/arch')
0 files changed, 0 insertions, 0 deletions