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author | Min Kyu Jeong <minkyu.jeong@arm.com> | 2010-08-23 11:18:42 -0500 |
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committer | Min Kyu Jeong <minkyu.jeong@arm.com> | 2010-08-23 11:18:42 -0500 |
commit | e6a0be648e9fdb4b882cfb5f3224d097817338bc (patch) | |
tree | c17014be98d173b862f1edabf2ca134e30184853 /src/arch | |
parent | d2fac84b95e778749606d5eeb15af906ba9e072e (diff) | |
download | gem5-e6a0be648e9fdb4b882cfb5f3224d097817338bc.tar.xz |
ARM: Improve printing of uop disassembly.
Diffstat (limited to 'src/arch')
-rw-r--r-- | src/arch/arm/insts/macromem.cc | 27 | ||||
-rw-r--r-- | src/arch/arm/insts/macromem.hh | 4 |
2 files changed, 31 insertions, 0 deletions
diff --git a/src/arch/arm/insts/macromem.cc b/src/arch/arm/insts/macromem.cc index e47f4c21c..2a2412912 100644 --- a/src/arch/arm/insts/macromem.cc +++ b/src/arch/arm/insts/macromem.cc @@ -215,4 +215,31 @@ MacroVFPMemOp::MacroVFPMemOp(const char *mnem, ExtMachInst machInst, } } +std::string +MicroIntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +{ + std::stringstream ss; + printMnemonic(ss); + printReg(ss, ura); + ss << ", "; + printReg(ss, urb); + ss << ", "; + ccprintf(ss, "#%d", imm); + return ss.str(); +} + +std::string +MicroMemOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +{ + std::stringstream ss; + printMnemonic(ss); + printReg(ss, ura); + ss << ", ["; + printReg(ss, urb); + ss << ", "; + ccprintf(ss, "#%d", imm); + ss << "]"; + return ss.str(); +} + } diff --git a/src/arch/arm/insts/macromem.hh b/src/arch/arm/insts/macromem.hh index f2d4f9276..003f5a3fd 100644 --- a/src/arch/arm/insts/macromem.hh +++ b/src/arch/arm/insts/macromem.hh @@ -94,6 +94,8 @@ class MicroIntOp : public MicroOp ura(_ura), urb(_urb), imm(_imm) { } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; /** @@ -111,6 +113,8 @@ class MicroMemOp : public MicroIntOp up(_up), memAccessFlags(TLB::MustBeOne | TLB::AlignWord) { } + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; /** |