diff options
| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-02-18 14:33:36 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-04-02 16:20:54 +0000 |
| commit | e7a1636889dec63a65723dc4df71d1970b013116 (patch) | |
| tree | 3022c888d5365ae83faf64468264bb015e47f48b /src/arch | |
| parent | 4628d87e3abbcad0c5a95b6a4562b8ac8c6f4661 (diff) | |
| download | gem5-e7a1636889dec63a65723dc4df71d1970b013116.tar.xz | |
dev-arm: Make GICv3 maintenance interrupt an ArmInterrupt
Change-Id: I88e2b72849cdf3f69026c62517303837e7d3d551
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17629
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/arm/isa.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 38fbae142..42e1cba3f 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -403,6 +403,7 @@ ISA::startup(ThreadContext *tc) haveGICv3CPUInterface = true; gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId())); gicv3CpuInterface->setISA(this); + gicv3CpuInterface->setThreadContext(tc); } } } |