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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-08-20 11:24:40 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-09-06 11:53:49 +0000 |
| commit | ead1e7a2a36a1d5fd1c612554590c99a05a98ce4 (patch) | |
| tree | 387cacbdff712f8c2e7e375ab2bbdc60407cc372 /src/arch | |
| parent | 51022bfe0eeaef5f08d6ace98ebfb1917d1b3331 (diff) | |
| download | gem5-ead1e7a2a36a1d5fd1c612554590c99a05a98ce4.tar.xz | |
dev-arm: Rewrite ICC_BPR0/ICC_BPR1 handling
The patch is fixing BPR reads in AA32, by removing the line
Gicv3::GroupId group =
misc_reg == MISCREG_ICC_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1S;
Where a read to ICC_BPR0 will return a G1S group.
The patch is also fixing Security banking accesses.
Change-Id: I28f1d1244c44d4b8b202d3141f8380943c7c1c86
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20620
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch')
0 files changed, 0 insertions, 0 deletions